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The following pictures show the pin assignment for programming Xilinx respectively Lattice CPLD's using Seco's JTAG debug PCB by Keith & Koep.
Xilinx CPLD
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Lattice CPLD
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The following pictures show the pin assignment for programming Xilinx respectively Lattice CPLD's using Seco's JTAG debug PCB by Keith & Koep.
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