Customers may request access to the source-code of the firmware to modify it for their needs.
Commands & Registers (I2C)
I2C-Address: 0x40 (7-bit) | |||||
Register | Name | Access | Description | Default Value | |
0x01 | REG_ID | read | ID-Register | 0x96 | |
0x02 | REG_CONTROL | write | Restart and boot with BOOT_MODE= 0x04 - Shutdown (Hard) | - | |
0x03 | REG_CONFIG | - | - | - | |
0x04 | REG_PIN_CONFIG | write | <Pin> <Parameter> 0x01: Input, NoPull 0x20: Output PushPull, init low level 0x80: IRQ Rising Edge | - | |
0x05 | REG_PIN_SET | write | <Pin> <Level> | - | |
0x06 | REG_PIN_GET | write | <Pin> | - | |
0x07 | REG_PWM_CONFIG | write | <Pin> <Duty Cycle [%]> | - | |
0x08 | REG_SECO_CODE | read | Read bits [7:0] of SECO_CODE. | - | |
0x09 | REG_RAM_CODE | read | Read RAM_CODE [3:0]. 0x4 - 4GB RAM | - | |
0x0A | REG_ALTERNATE_ | write | Set Pin to specific alternate function. <Pin> <Alternate Function> Alternate Functions: | ||
0x0B0x09 | REG_ADC_READ | read | Read ADC value: 0x01 0x00 - ADC_VOLT_MON (=5V_SLEEP/2) | - | |
0x0C0x0A | REG_INT_STATUS0 | read | Read INT_STATUS register, clear it and reset EC_IRQ#_OD to “1” 0x01: GPIO4 | 0x00 | |
0x0D0x0B | REG_INT_ENABLE0 | write | Enable interruptsr/w | Read or update IRQ Enable Register. Same signals as in REG_INT_STATUS1STATUS0. | 0x00 |
0x0E0x0C | REG_INT_STATUS1 | read | Read INT_STATUS2 register, clear it and reset EC_IRQ#_OD to “1” if all interrupts are read. 0x01: USB0USB1_EN_OC# | 0x00 | |
0x0F0x0D | REG_INT_ENABLE1 | write | Enable interruptsr/w | Read or update IRQ Enable Register. Same signals as in REG_INT_STATUS2STATUS1. | 0x00 |
0x100x0E | REG_INT_STATUS2 | - | - | ||
0x110x0F | REG_INT_ENABLE2 | - | - | 0x12 | |
0x10 | REG_SHUTDOWN_DELAY | r/w | Read/write delay in 10ms steps before powering off during soft shutdown/restart. (0x01 = 10ms, 0xFF = 2550 ms) | ||
0x80 | REG_SECO_CODE0 | read | Read bits [7:0] of SECO_CODE. | - | |
0x81 | REG_SECO_CODE1 | read | Read bits [11:8] of SECO_CODE. | ||
0x90 | REG_RAM_CODE | read | Read RAM_CODE [3:0]. 0x4 - 4GB RAM | - | |
0xF0 | REG_VERSION | read | Read firmware version | 0x01 | |
Configurable GPIO Pins (I2C)
The following Pins are configurable via I2C:
Pin# | Name | Default Configuration | IRQ | Alternate Function | ||||
|---|---|---|---|---|---|---|---|---|
0 | GPIO4 | Input, NoPull |
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1 | GPIO5 | PWMInput, 0% duty cycleNoPull |
| GPIOPWM | ||||
2 | GPIO6GPIO11 | Input, NoPull |
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3 | GPIO11GPIO12 | Input, NoPull |
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4 | GPIO12GPIO13 | Input, NoPull |
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5 | GPIO13 | Input, NoPull |
| 6 | RTC_INT# | (IRQ only) |
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76 | SMB_ALERT# | (IRQ only) |
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87 | USB0_EN_OC# | Output, OpenDrain, init low level |
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98 | USB1_EN_OC# | Output, OpenDrain, init low level |
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109 | USB2_EN_OC# | Output, OpenDrain, init low level |
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1110 | CPU_IRQ# | (IRQ only) |
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1211 | USB_HUB_RST# | Output, PushPull, init low level | ||||||
1312 | WIFI_PWRDWN# | Output, PushPull, init low level | ||||||
1413 | BATLOW# | Input, NoPull | ||||||
1514 | CHARGING# | Input, NoPull | ||||||
1615 | CHARGER_PRSNT# | Input, NoPull | ||||||
1716 | RESET_OUT# | Output, PushPull, init low level, set high ~100ms after startup (-> SMARC Spec.) |
*: Polled IRQ
Carrier board BOOT_SEL configuration
The BOOT_SEL[2:0] Configuration on the carrier board is used to determine whether the system will boot into serial download mode or attempt to boot from eMMC:
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Connecting FORCE_RECOV# to GND will cause the STM32 to always set the BOOT_MODE to Serial Dwonload Mode.
Other Functions
Pressing the POWER button for <10 seconds while the system is running (if 1V8_RUN is enabled and Linux is running) triggers a soft shutdown.
Holding the POWER button for >= 10 seconds will cause the system to shut down hard.
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