Page Comparison

Please view the Trizeps VIII FPGA page.
This page will only point out differences between Trizeps VIII and Trizeps VIII Nano FPGA.

...

• Programming

• Firmware

  • Default-Firmware

  • Read Version

• Download

http://gitlab.keith-koep.com/tr8firmware/tr8_fpga

The Trizeps VIII can be equipped with a Lattice MachXO3 FPGA with either 640, 1300, 2100 or 4300LUT.

Programming

The FPGA may be programmed through JTAG using connector J401 (see datasheet for details) or in system through I2C.
In-System-Programming through I2C has not been verified yet.

MachXO3 FPGAs are available in two different programmable-versions:

• Multi-Programmable: LCMXO3L up to 9 times programmable

• Programmable Flash: LCMXO3LF 100.000 write/erase-cycles

Firmware

The Trizeps VIII is able to boot without any firmware programmed to the FPGA.

Customers may request access to the source-code of the firmware to modify it for their needs.

Default-Firmware

The following describes the current default-firmware, which is designed to offer best compatibility to previous Trizeps modules functionality and Seco baseboards.

 Display-Control-Register for
 MIPI-DSI to parallel RGB converter
 0x8.   Invert Pixel-Clock polarity
 0x4.   Invert HSync polarity
 0x2.   Invert VSync polarity
 0x1.   Invert DE polarity
 0x.C   Use RGB24, LCD_D[23..0]
 0x.8   Use RGB18, LCD_D[17..0]
 0x.4   Use RGB16, LCD_D[15..0]
 0x.1   Enable converter

 Pin-Mux-Control-Register
 0x.0   UART4/SPI2 not routed.
 0x.1   UART4 routed to on-board 
        BT-module.
 0x.2   SPI2 routed to SODIMM
        (Pins: 86 SS,88 CLK,90 MISO,92 MOSI)
 0x.3   SPI2 routed to SODIMM
        (Pins: 170 MOSI,172 CLK,178 SS,180 MISO)
 0x.4   SPI2 routed to SODIMM
        (Pins: 170 MISO,172 SS,178 CLK,180 MOSI)

 Read Version of FPGA-Code

Read Version

The currently programmed version can be read in bootloader through:

u-boot=> i2c dev 2
u-boot=> i2c md 0x41 F0.1 1

or in linux through:

i2cget -f -y 2 0x41 0xf0

Versions prior to version 1 return „read failure“ on attempt to read register 0xF0.

Download

 + Added I2C_REG_VERSION 
 + Added option 4 & fixed option 3 of I2C_REG_PINMUX
 + Add extra display-reset condition.

 + Fix routing of SPI/BTUART pins.

 + Disable clamping of pins on VDD_FPGA_MIPI power-domain.

 + Changed I2C_SCL and I2C_SDA to OpenDrain.

 Firmware for LCMXO3LF-2100E-6MG121C
 + Added supervisor to check wether valid display-data is received
   and if not reset receive-part.