Trizeps VIII

 

 

 

 

Depending on configuration and following revisions, the board’s features are subject to change. Please visit www.seconorth.com to find updated information.

 

1. Description

The Trizeps VIII is powered by NXP i.MX 8M processor, which is designed to meet the latest market requirements of connected streaming audio/video devices, scanning/imaging devices and various devices demanding high-performance and low-power.

The i.MX 8M family of processors features advanced implementation of a quad ARM® Cortex®-A53 core, which operates at speeds of up to 1.5GHz (consumer version) and 1.3GHz (industrial version). A general purpose Cortex®-M4 core processor is for low-power processing. A 32-bit LPDDR4 is used for memory. There are a number of other i.MX 8M interfaces for connecting peripherals, such as displays, cameras, GPS and sensors, which are extended by components already available on the module:

  • a stereo, hi-fi quality audio-codec.

  • FPGA with up to 4300 LUT to convert parallel display/camera/data-streams to/from MIPI and for user defined programmable logic.

  • a programmable Cortex-M0 Kinetis MCU for realtime processing, capable of reading multiple 16bit analog inputs, usable as resistive touch-controller and for CAN communication.

  • WLAN 802.11 a/b/g/n/ac and Bluetooth 4.2 and 5 ready module

The Trizeps VIII module got a SODIMM200 card edge connector and a 60pin FX11 high-speed board connector. The pinning of both connectors is to a large extent compatible to previous Trizeps modules. The main difference is the new USB3.0 SuperSpeed and GBit Ethernet feature, which use the pins of the now missing parallel address-/databus.

Difference to Trizeps VIII Mini

The i.MX8M Mini processor of Trizeps VIII Mini benefits from advanced 14nm LPC FinFET Technology, which allows for lesser power-consumption and higher operating frequencies than the i.MX8 used on Trizeps VIII.

But the Trizeps VIII offers more interfaces:

  • HDMI

  • support for 4K displays.

  • two USB3.0 instead of USB2.0 ports.

  • additional 4ch MIPI CSI port.

  • larger L2 cache.

The GPIO pinning between both modules is kept the same for maximum compatibility.


2. Technical Info

 

Block Diagram