SOM-Trizeps-VIII-MX8M-Plus ( Trizeps VIII Plus )
- 1 Description
- 2 Features and Interfaces
- 2.1 Features
- 2.2 Processor:
- 2.3 Memory:
- 2.4 Storage:
- 2.5 Wireless:
- 2.6 Power:
- 2.7 Dimensions:
- 2.8 Interfaces / Signals accessible over connectors
- 3 1 Pin-description
- 4 2 Interfaces
- 4.1 2.1 Power Supply
- 4.2 2.2 Control-Signals
- 4.3 2.3 UART
- 4.4 2.4 SPI
- 4.5 2.5 QSPI
- 4.6 2.6 I2C
- 4.7 2.7 I2S
- 4.8 2.8 SD-Card
- 4.9 2.9 USB
- 4.10 2.10 PCIe
- 4.11 2.11 Ethernet
- 4.12 2.12 CAN
- 4.13 2.13 Display
- 4.13.1 2.13.1 DSI-MIPI (4ch)
- 4.13.2 2.13.2 Single-/Dual LVDS
- 4.13.3 2.13.3 Parallel RGB Display
- 4.13.4 1.13.4 HDMI
- 4.14 2.14 Camera
- 4.15 2.15 Wireless
- 4.16 2.16 Audio
- 4.17 2.17 SPDIF
- 4.18 2.18 Secure Element
- 5 3 Specifications
- 6 4 Article numbers for Trizeps VIII Plus
- 7 5 Important Notice
- 8 6 Document History
Description
The Trizeps VIII Plus is powered by NXP i.MX 8M Plus processor, which is designed to meet the latest market requirements of connected streaming audio/video devices, scanning/imaging devices and various devices demanding high-performance and low-power. It offers a 2.3 TOP/s Neural Processing Unit (NPU) for AI-applications like pattern, object and speech recognition.
The i.MX 8M Plus family of processors features advanced implementation of a quad ARM® Cortex®-A53 core, which operates at speeds of up to 1.8GHz (consumer version) and 1.6GHz (industrial version). A general purpose Cortex®-M7 core processor is for low-power processing. A 32-bit LPDDR4 is used for memory. There are a number of other i.MX 8M Plus interfaces for connecting peripherals, such as displays, cameras, GPS and sensors, which are extended by components already available on the module:
a stereo, hi-fi quality audio-codec.
a FPGA with up to 4300 LUT to convert MIPI-DSI to parallel 24bpp display data and for user defined programmable logic.
a programmable Cortex-M0 Kinetis MCU, capable of realtime processing, reading multiple 16bit analog inputs or usable as resistive touch-controller.
WLAN 802.11 a/b/g/n/ac and BT 4.2 / 5 module
The Trizeps VIII Plus module got a SODIMM200 card edge connector and a 60pin FX11 high-speed board connector. The pinning of both connectors is to a large extent compatible to previous Trizeps modules.
Difference to Trizeps VIII
The i.MX 8M Plus processor of Trizeps VIII Plus benefits from advanced 14nm LPC FinFET Technology, which allows for lesser power-consumption and higher operating frequencies than the i.MX8 used on Trizeps VIII.
The Trizeps VIII offers:
support of 4K displays
It misses following features:
2.3 TOP/s NPU (Neural Processing Unit)
2x CAN
second Ethernet-MAC
third SDIO-port routed to SODIMM
Difference to Trizeps VIII Mini
The i.MX 8M Mini processor of Trizeps VIII Mini can be considered as the predecessor to the i.MX 8M Plus processor used on Trizeps VIII Plus.
The Trizeps VIII Mini lacks some of the interfaces:
2.3 TOP/s NPU (Neural Processing Unit)
2x CAN
second Ethernet-MAC
third SDIO-port routed to SODIMM
HDMI
multi-display support: only MIPI-DSI or LVDS may be used at the same time.
only USB2.0, instead of USB3.0 ports.
Block Diagram
Technical Documents
Manual:
Changes of key components over the revisions
| Ethernet PHY | Audio Codec |
---|---|---|
V1R1 | Qualcomm AR8031 | Cirrus WM8983 |
V1R2 | Qualcomm AR8031 | Cirrus WM8983 |
V1R3 | REALTEK RTL8211 | Cirrus WM8962 |
V1R4 | REALTEK RTL8211 | Cirrus WM8962 |
Features and Interfaces
Features
Processor:
NXP i.MX 8M Plus ARM® Quad Cortex-A53 at up to 1.8GHz (consumer), 1.6GHz (industrial)
NXP i.MX 8M Plus ARM® Cortex-M7 at up to 800MHz
Neural Processing Unit 2.3 TOPS
NXP Kinetis V ARM® Cortex-M0+ at up to 75MHz
Memory:
Up to 8 GByte of 32-bit LPDDR4-4000
Storage:
Micro-SD socket or
4 or 8 GByte eMMC
Higher densities are available on request.
Wireless:
WLAN 802.11 a/b/g/n/ac
BT 4.2 and BT 5.0
Micro RF-antenna connector
Power:
PMIC to generate all internal and external voltages from VSYS supply.
Dimensions:
(Length x Width x Height): 67.6 x 36.7 x 6.4 mm
Interfaces / Signals accessible over connectors
Power Supply from +3.3V to +5V
2x USB3.0 OTG port (USB Host or Slave)
PCIe
2x SD/SDIO Card Interface
4x UART
SPI and Quad-SPI
2x I2C
MIPI Display (4ch) or parallel RGB Display
Single/Dual LVDS
HDMI
2x Mipi Camera (4ch)
1000/100/10Mbit Ethernet
2x CAN/CAN-FD
2x 4ch 16bit ADC
Stereo Headphone
Stereo Line-In
Microphone input (mono, optional stereo)
1W Speaker output
SPDIF In and Out
Multi-Channel Serial-Audio-Interface
GPIO, PWM
1 Pin-description
The main connector of the Trizeps VIII Plus is the SODIMM200 connector.
To operate, only VSYS and GND pins need to be connected. Leave unused pins unconnected.
The U14 Board2Board connector can be omitted if the signals are not needed.
J1 and J2 may be used for debugging, programming and testing.
On the bottom side are UFL antenna connectors for the on-board WLAN + BT- chip.
1.1 Pin-description (Primary Function)
The i.MX8M Plus processor, the Cortex M0+ MCU and the FPGA are highly configurable devices, where each pin may have multiple different functions.
The pin-names are derived from previous Trizeps-versions and their primary or most interesting function.
Please view chapter “1.2 Pin-Mux Information” for details on how these pins may be configured by software.
Notes:
*1) In the table below, some of the old Trizeps pin-names are placed in brackets [] for reference.
*2) FPGA_CIF_D[9..0] / SAIx_RXD[7..0], FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are routed to the FPGA and the i.MX 8M Plus. In the following documentation they are either named FPGA_CIF_Dx or SAIx_RXDy, depending if the FPGA or i.MX 8M Plus function is described.
*3) FPGA_CIF_VSYNC, FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are connected to i.MX 8M Plus pins, if the FPGA is not mounted (RA72).
*4) BT_PCM_IN, BT_PCM_OUT, BT_PCM_SYNC and BT_PCM_CLK are connected to the on-board BT-module if it is mounted!
*5) PCIE_CLKREQ may not be usable when Wifi module is mounted.
J1: SODIMM Connector
Signal | Pin |
| Pin | Signal |
AUDIO_MIC_OUT | 1 |
| 2 | VIN_AD3 (MCU) |
AUDIO_MIC_GND | 3 |
| 4 | VIN_AD2 (MCU) |
AUDIO_LINEIN_L | 5 |
| 6 | VIN_AD1 (MCU) |
AUDIO_LINEIN_R | 7 |
| 8 | VIN_AD0 (MCU) |
AUDIO_AGND | 9 |
| 10 | AUDIO_VDDA |
AUDIO_AGND | 11 |
| 12 | AUDIO_VDD_SPEAKER |
AUDIO_HEADPHONE_GND | 13 |
| 14 | TSPX (MCU) |
AUDIO_HEADPHONE_L | 15 |
| 16 | TSMX (MCU) |
AUDIO_HEADPHONE_R | 17 |
| 18 | TSPY (MCU) |
UART3_RXD | 19 |
| 20 | TSMY (MCU) |
UART3_TXD | 21 |
| 22 | SPIN22_RTS3 |
UART1_DTR | 23 |
| 24 | SPIN24_CTS3 |
UART1_CTS | 25 |
| 26 | RESET_IN |
UART1_RTS | 27 |
| 28 | SPEAKER_R |
UART1_DSR | 29 |
| 30 | SPEAKER_L |
UART1_DCD | 31 |
| 32 | UART2_CTS |
UART1_RXD | 33 |
| 34 | UART2_RTS |
UART1_TXD | 35 |
| 36 | UART2_RXD |
UART1_RI | 37 |
| 38 | UART2_TXD |
GND | 39 |
| 40 | VSYS (+3V3/+5V) |
GND | 41 |
| 42 | VSYS (+3V3/+5V) |
SPIN43 | 43 |
| 44 | LCD_EN |
SPIN45 | 45 |
| 46 | LCD_D07 |
SD2_CLK | 47 |
| 48 | LCD_D09 |
CIF_D0 | 49 |
| 50 | LCD_D11 |
SD2_DATA3 | 51 |
| 52 | LCD_D12 |
CIF_D1 | 53 |
| 54 | LCD_D13 |
SPIN55 | 55 |
| 56 | LCD_PCLK |
SAI1_RXD2 | 57 |
| 58 | LCD_D03 |
SD2_DETECT | 59 |
| 60 | LCD_D02 |
SAI1_RXD3 | 61 |
| 62 | LCD_D08 |
SAI1_RXD4 | 63 |
| 64 | LCD_D15 |
SAI1_RXD5 | 65 |
| 66 | LCD_D14 |
SAI1_RXD6 | 67 |
| 68 | LCD_HSYNC |
LED_GPIO | 69 |
| 70 | LCD_D01 |
SAI1_RXD7 | 71 |
| 72 | LCD_D05 |
CIF_D8 | 73 |
| 74 | LCD_D10 |
CIF_D9 | 75 |
| 76 | LCD_D00 |
BACKLIGHT_PWM | 77 |
| 78 | LCD_D04 |
POWERFAIL | 79 |
| 80 | LCD_D06 |
SD2_DATA1 | 81 |
| 82 | LCD_VSYNC |
GND | 83 |
| 84 | VSYS (+3V3/+5V) |
SD2_DATA2 | 85 |
| 86 | CIF_VSYNC (*3) |
RESET_OUT | 87 |
| 88 | CIF_MCLK (*3) |
+3V3_AUX | 89 |
| 90 | CIF_PCLK (*3) |
+3V3_AUX | 91 |
| 92 | CIF_HSYNC (*3) |
N.C. | 93 |
| 94 | I2C1_SCL |
SPIN95 [RDY] | 95 |
| 96 | I2C1_SDA |
CAN1_RX | 97 |
| 98 | GPIO_AUX |
CAN1_TX | 99 |
| 100 | DISPLAY_ENABLE |
CAN2_RX | 101 |
| 102 | AUDIO_ENABLE |
CAN2_TX | 103 |
| 104 | SPIN104 |
QSPI_SCLK [CS1] | 105 |
| 106 | VSD_3V3 |
QSPI_SS0 [CS3] | 107 |
| 108 | VSYS (+3V3/+5V) |
GND | 109 |
| 110 | SAI1_TXD0 |
QSPI_DATA0 [A00] | 111 |
| 112 | SAI1_TXD1 |
QSPI_DATA1 [A01] | 113 |
| 114 | SAI1_TXD2 |
PCIE_CLKREQ (*5) | 115 |
| 116 | SAI1_TXD3 |
QSPI_DATA2 [A03] | 117 |
| 118 | SAI1_TXD4 |
QSPI_DATA3 [A04] | 119 |
| 120 | SAI1_TXD5 |
SPIN121 [A05] | 121 |
| 122 | SAI1_TXD6 |
CSI1_PWDN [A06] | 123 |
| 124 | SAI1_TXD7 |
CSI1_RESET [A07] | 125 |
| 126 | SAI1_TXFS |
USB1_PEN | 127 |
| 128 | SAI1_TXC |
USB2_PEN | 129 |
| 130 | HDMI_DDC_SCL |
USB2_OC | 131 |
| 132 | N.C. |
USB1_OC | 133 |
| 134 | SPIN134 |
USB1_VBUS | 135 |
| 136 | SPIN136 |
USB1_ID | 137 |
| 138 | USB1_RXP |
USB1_DP | 139 |
| 140 | USB1_RXN |
USB1_DN | 141 |
| 142 | USB1_TXP |
USB2_DP | 143 |
| 144 | USB1_TXN |
USB2_DN | 145 |
| 146 | BT_PCM_IN (*4) |
GND | 147 |
| 148 | VSYS (+3V3/+5V) |
HDMI_DDC_SDA | 149 |
| 150 | LCD_D16 |
USB2_TXP | 151 |
| 152 | LCD_D17 |
USB2_TXN | 153 |
| 154 | PCIE_WAKE |
USB2_RXP | 155 |
| 156 | VDD_FPGA_MIPI |
USB2_RXN | 157 |
| 158 | PCIE_CLK_N |
SPDIF_IN [D05] | 159 |
| 160 | PCIE_CLK_P |
SPDIF_OUT [D06] | 161 |
| 162 | PCIE_TX_P |
SPDIF_EXT_CLK [D07] | 163 |
| 164 | PCIE_TX_N |
LED_WL | 165 |
| 166 | PCIE_RX_P |
LED_BT [D09] | 167 |
| 168 | PCIE_RX_N |
VDD_ENET_IO [D10] | 169 |
| 170 | FPGA_LCD_D21 or SD3_DATA0 |
ETH_LED_SPEED1000 [D11] | 171 |
| 172 | FPGA_LCD_D20 or SD3_DATA1 |
ETH_TRX2_N [D12] | 173 |
| 174 | FPGA_LCD_D19 or SD3_DATA2 |
ETH_TRX2_P [D13] | 175 |
| 176 | FPGA_LCD_D18 or SD3_DATA3 |
ETH_TRX3_N [D14] | 177 |
| 178 | FPGA_LCD_D23 or SD3_CLK |
ETH_TRX3_P [D15] | 179 |
| 180 | FPGA_LCD_D22 or SD3_CMD |
GND | 181 |
| 182 | VSYS (+3V3/+5V) |
ETH_LED_LINK_AKT | 183 |
| 184 | BT_PCM_OUT (*4) |
ETH_LED_SPEED100 | 185 |
| 186 | BT_PCM_CLK (*4) |
ETH_TRX0_N | 187 |
| 188 | BT_PCM_SYNC (*4) |
ETH_TRX0_P | 189 |
| 190 | SD2_CMD |
ETH_GND | 191 |
| 192 | SD2_DATA0 |
ETH_TRX1_N | 193 |
| 194 | I2C2_SDA |
ETH_TRX1_P | 195 |
| 196 | I2C2_SCL |
GND | 197 |
| 198 | VSYS (+3V3/+5V) |
GND | 199 |
| 200 | VCC_SNVS (+3V3) |
J2: Board2Board Connector
Signal | Pin |
| Pin | Signal |
MIPI_CSI1_D2_P | 1 |
| 2 | MIPI_DSI_D3_P |
MIPI_CSI1_D2_N | 3 |
| 4 | MIPI_DSI_D3_N |
MIPI_CSI1_D3_P | 5 |
| 6 | MIPI_DSI_D2_P |
MIPI_CSI1_D3_N | 7 |
| 8 | MIPI_DSI_D2_N |
MIPI_CSI2_CLK_P | 9 |
| 10 | LVDS1_TX2_P |
GND | 11 |
| 12 | GND |
MIPI_CSI2_CLK_N | 13 |
| 14 | LVDS1_TX2_N |
MIPI_CSI2_D0_P | 15 |
| 16 | LVDS1_TX3_N |
MIPI_CSI2_D0_N | 17 |
| 18 | LVDS1_TX3_P |
MIPI_CSI2_D1_P | 19 |
| 20 | LVDS1_CLK_P |
MIPI_CSI2_D1_N | 21 |
| 22 | LVDS1_CLK_N |
MIPI_CSI2_D2_P | 23 |
| 24 | LVDS1_TX0_P |
MIPI_CSI2_D2_N | 25 |
| 26 | LVDS1_TX0_N |
MIPI_CSI2_D3_P | 27 |
| 28 | LVDS1_TX1_P |
MIPI_CSI2_D3_N | 29 |
| 30 | LVDS1_TX1_N |
MIPI_DSI_D1_P | 31 |
| 32 | MIPI_DSI_D1_N |
GND | 33 |
| 34 | GND |
LVDS0_TX1_N | 35 |
| 36 | MIPI_DSI_CLK_N |
LVDS0_TX1_P | 37 |
| 38 | MIPI_DSI_CLK_P |
LVDS0_TX0_P | 39 |
| 40 | HDMI_TX1_P |
LVDS0_TX0_N | 41 |
| 42 | HDMI_TX1_N |
LVDS0_CLK_N | 43 |
| 44 | HDMI_TX2_P |
LVDS0_CLK_P | 45 |
| 46 | HDMI_TX2_N |
LVDS0_TX2_P | 47 |
| 48 | HDMI_HPD |
LVDS0_TX2_N | 49 |
| 50 | HDMI_CLK_N |
LVDS0_TX3_P | 51 |
| 52 | HDMI_CLK_P |
LVDS0_TX3_N | 53 |
| 54 | HDMI_CEC |
GND | 55 |
| 56 | GND |
MIPI_DSI_D0_N | 57 |
| 58 | HDMI_TX0_N |
MIPI_DSI_D0_P | 59 |
| 60 | HDMI_TX0_P |
MIPI_CSI1_D0_N | 61 |
| 62 | MIPI_CSI1_CLK_N |
MIPI_CSI1_D0_P | 63 |
| 64 | MIPI_CSI1_CLK_P |
MIPI_CSI1_D1_P | 65 |
| 66 | MIPI_CSI1_D1_N |
GND | 67 |
| 68 | GND |
J90: i.MX8M JTAG Connector
This flex-cable-connector uses the SECO Northern Europe JTAG connector standard. An Adapter to Multi-ICE pin-header is available.
Pin | Signal |
1 | +3V3 |
2 | GND |
3 | JTAG_TMS |
4 | N.C. |
5 | JTAG_TCK |
6 | JTAG_TDO |
7 | JTAG_TDI |
8 | JTAG_RESET_N |
J91: FPGA & MCU JTAG Connector
This flex-cable-connector uses the SECO Northern Europe JTAG connector standard. An adapter to Multi-ICE pin-header is available.
Pin | Signal |
1 | VDD_FPGA_MIPI |
2 | GND |
3 | FPGA_JTAG_TMS |
4 | SWD_CLK |
5 | FPGA_JTAG_TCK |
6 | FPGA_JTAG_TDO |
7 | FPGA_JTAG_TDI |
8 | SWD_DIO |
1.2 Pin-Mux Information
Several pins are GPIOs which may be configured for different functions by software.
Please check with the processor datasheet for additional pin-mux information.
An Excel-Sheet with pin-information is available at: https://documentation.seco.com/service/doku.php/service/hardware/module/sodimm200
Notes:
*3) FPGA_CIF_VSYNC, FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are connected to i.MX 8M Plus pins, if the FPGA is not mounted (RA72).
*4) BT_PCM_IN, BT_PCM_OUT, BT_PCM_SYNC and BT_PCM_CLK are connected to the on-board BT-module if it is mounted!
*5) PCIE_CLKREQ may not be usable when Wifi module is mounted.
1.2.1 i.MX 8M Plus pins
The i.MX 8M Plus pins got up to 10 different functions. Only the more common used are listed.
PIN | Name | Alt0 | Alt1 | Alt2 / Alt3 | Alt5 |
19 | UART3_RXD | ecspi1.SCLK | uart3.RX |
| gpio5.IO[6] |
21 | UART3_TXD | ecspi1_MOSI | uart3.TX |
| gpio5.IO[7] |
22 | SPIN22_RTS3 | ecspi1.MISO | uart3.CTS_B |
| gpio5.IO[8] |
23 | UART1_DTR | sai5.RX_SYNC | sai1.TX_DATA[0] |
| gpio3.IO[19] |
24 | SPIN24_CTS3 | ecspi1.SS0 | uart3.RTS_B |
| gpio5.IO[9] |
25 | UART1_CTS | uart3.TX | uart1.RTS_B |
| gpio5.IO[27] |
27 | UART1_RTS | uart3.RX | uart1.CTS_B |
| gpio5.IO[26] |
29 | UART1_DSR | sai5.RX_BCLK | sai1.TX_DATA[1] |
| gpio3.IO[20] |
31 | UART1_DCD | sai2.RX_SYNC | sai5.TX_SYNC | sai5.TX_DATA[1] | gpio4.IO[21] |
32 | UART2_CTS | uart4.TX | uart2.RTS_B |
| gpio5.IO[29] |
33 | UART1_RXD | uart1.RX | ecspi3.SCLK |
| gpio5.IO[22] |
34 | UART2_RTS | uart4.RX | uart2.CTS_B | pcie1.CLKREQ_B | gpio5.IO[28] |
35 | UART1_TXD | uart1.TX | ecspi3.MOSI |
| gpio5.IO[23] |
36 | UART2_RXD | uart2.RX | ecspi3.MISO |
| gpio5.IO[24] |
37 | UART1_RI | sai2.RX_BCLK | sai5.TX_BCLK |
| gpio4.IO[22] |
38 | UART2_TXD | uart2.TX | ecspi3.SS0 |
| gpio5.IO[25] |
43 | SPIN43 | gpio1.IO[7] |
|
| usdhc1.WP |
45 | SPIN45 | rawnand.CE3_B | qspi.B_SS1_B |
| gpio3.IO[4] |
47 | SD2_CLK | usdhc2.CLK |
|
| gpio2.IO[13] |
49 | SAI1_RXD0 | sai1.RX_DATA[0] | sai5.RX_DATA[0] | sai1.TX_DATA[1] | gpio4.IO[2] |
51 | SD2_DATA3 | usdhc2.DATA3 |
|
| gpio2.IO[18] |
53 | SAI1_RXD1 | sai1.RX_DATA[1] | sai5.RX_DATA[1] |
| gpio4.IO[3] |
55 | SPIN55 | sai5.RX_DATA[0] | sai1.TX_DATA[2] |
| gpio3.IO[21] |
57 | SAI1_RXD2 | sai1.RX_DATA[2] | sai5.RX_DATA[2] | enet1_MDC | gpio4.IO[4] |
59 | SD2_DET | usdhc2.CD_B |
|
| gpio2.IO[12] |
61 | SAI1_RXD3 | sai1.RX_DATA[3] | sai5.RX_DATA[3] | enet1_MDIO | gpio4.IO[5] |
63 | SAI1_RXD4 | sai1.RX_DATA[4] | sai6.TX_BCLK | enet1_RD0 | gpio4.IO[6] |
65 | SAI1_RXD5 | sai1.RX_DATA[5] | sai6.TX_DATA[0] | sai1.RX_SYNC | gpio4.IO[7] |
67 | SAI1_RXD6 | sai1.RX_DATA[6] | sai6.TX_SYNC | sai6.RX_SYNC | gpio4.IO[8] |