Technical introduction SOM-SMARC-QCS5430/6490
- 1.1 Generals
- 1.2 Description
- 1.3 SMARC Standard
- 1.4 Blockdiagram
- 2 Features and Interfaces
- 2.1 Features
- 2.1.1 Processor
- 2.1.2 Memory
- 2.1.3 Storage
- 2.1.4 Wireless (optional)
- 2.1.5 Power
- 2.1.6 Dimensions
- 2.1.7 Interfaces / Signals accessible over connector
- 2.1 Features
- 3 Technical Documents
- 4 1. Pin description
- 5 2. Interfaces
- 5.1.1 2.1 Power Supply
- 5.1.1.1 Table 4: Power Supply pins
- 5.1.2 2.3 UART
- 5.1.2.1 Table 7: UART pins
- 5.1.3 2.4 SPI
- 5.1.3.1 Table 8: SPI pins
- 5.1.4 2.6 I2C
- 5.1.4.1 Table 9: I2C pins
- 5.1.5 2.7 I2S
- 5.1.5.1 Table 10: I2S pins
- 5.1.6 2.8 SDIO
- 5.1.6.1 Table 11: SDIO pins
- 5.1.7 2.9 USB
- 5.1.7.1 Table 12: USB pins
- 5.1.8 2.10 Ethernet
- 5.1.9 2.11 CAN
- 5.1.9.1 Table 14: CAN pins
- 5.1.10 2.12 Display
- 5.1.11 2.12.1 LVDS display or eDP (optional)
- 5.1.11.1 Table 15: LVDS or eDP pins
- 5.1.12 2.12.2 LVDS
- 5.1.12.1 Table 16: LVDS
- 5.1.1 2.1 Power Supply
- 5.2 2.13 Recommended Operating Conditions
Generals
Description
QCS6490 and QCS5430 are chipsets that deliver premium features with advanced camera, AI, and compute for high performance at low-power. These chipsets are built for industrial and commercial IoT applications such as ruggedized handhelds and tablets, kiosks, industrial scanners, point of sale systems, human machine interface systems, robotics, drone and controllers, cameras, and edge AI boxes.
SMARC Standard
The SMARC (“Smart Mobility ARChitecture”) is a versatile small form factor computer Module definition targeting applications that require low power, low costs, and high performance. The Modules will typically use ARM SOCs similar or the same as those used in many familiar devices such as tablet computers and smart phones. Alternative low power SOCs and CPUs, such as tablet oriented x86 devices and other RISC CPUs may be used as well.
The Module power envelope is typically under 6W although designs up to about 15W are possible.
Blockdiagram
Features and Interfaces
Features
Processor
Qualcomm QCS Family:
QCS5430 (FP1) (Total 6 cores)
Kryo Gold: 2 x CPU subsystem based on A78 at 2.13 GHz
Kryo Silver: 4 x CPU subsystem based on A55 at 1.8 GHz
QCS5430 (FP2) ( Total 6 cores)
Kryo Prime: 1 x CPU subsystem based on A78 at 2.2 GHz
Kryo Gold: 3 x CPU subsystem based on A78 at 2.13 GHz
Kryo Silver: 4 x CPU subsystem based on A55 at 1.8 GHz
QCS6490 (total
Kryo Prime: 1 CPU subsystem based on A78 at 2.7 GHz
Kryo Gold: 3 x CPU subsystem based on A78 at 2.4 GHz
Kryo Silver : 4 x CPU subsystem based on A55 at 1.9 GHz
Graphics
Integrated Graphics Processing Unit Qualcomm® Adreno™ 642L (QCS5430)
Integrated Graphics Processing Unit Qualcomm® Adreno™ 643L(QCS6490)
supports 2 independent displays, OpenGL , Open CL , Vulkan.
Embedded VPU
supports H/W decoding of HEVC/H.265, AVC/H.264
supports H/W encoding of HEVC/H.265, AVC/H.264
Video Interfaces
LVDS dual channel 18/24 bit, eDP V1.4, MIPI DSI 4 lanes,
Display Port through USB 3.1 Type C
Video Resolution
Primary display: FHD+ @120 fps
Secondary display: up to 4k Ultra HD @60Hz
Memory
Up to 12GByte of 64-bit LPDDR5-6400
Storage
Up to 64 GByte eMMC
Wireless (optional)
WLAN 802.11 a/b/g/n/ac/ax
BT 5.3
MicroRF-antenna connector
Power
PMIC to generate all internal and external voltages from 3.3V up to 5V supply.
Dimensions
(Length x Width x Height): 82.0 x 50.0 x 5.4 mm
Interfaces / Signals accessible over connector
Power Supply through 5.0VDC +- 5%, +3.2V_RTC
LVDS Dual Channel or eDP (factory alternatives) up to 2560x1600p60
HDMI or DP (factory alternatives) up to 4K60
SD 4-bit interface (usable as boot device)
2x Gigabit Ethernet interfaces
1x USB 2.0 OTG port
1x USB 3.1
up to 4x USB 2.0 using optional internal 2.0 Hub
1x I2S port
2x UART (4-wires)
2x UART (2-wires)
1x CAN interfaces (via SPI CAN Controller)
13x GPIOs
1 x MIPI_CSI0 2 Lanes Camera interface
2 x MIPI_CSI1 4 Lanes Camera Interface
1x General Purpose I2C Bus
2x PWM ports
TPM
Technical Documents
1. Pin description
The main connector of the SOM-SMARC- QCS 5430/6490 is the J2800 SMARC connector.
J500 may be used for debugging, programming and testing.
J700 is connection of a third camera.
On the top side are UFL antenna connectors for the on-board WLAN + BT chip.
1.1 Pin description
The following signals are present at the SMARC connector.
Table 1: SMARC connector CN2
Signal | Pin |
| Pin | Signal |
|---|---|---|---|---|
|
|
| S1 | I2C6_SCL |
SMB_ALERT# | P1 |
| S2 | I2C6_SDA |
GND | P2 |
| S3 | GND |
CSI1_CK_P | P3 |
| S4 | - |
CSI1_CLK_N | P4 |
| S5 | I2C5_SCL |
- | P5 |
| S6 | - |
- | P6 |
| S7 | I2C5_SDA |
CSI1_RX0_P | P7 |
| S8 | CSI0_CK_P |
CSI1_RX0_N | P8 |
| S9 | CSI0_CK_N |
GND | P9 |
| S10 | GND |
CSI1_RX1_P | P10 |
| S11 | CSI0_RX0_P |
CSI1_RX1_N | P11 |
| S12 | CSI0_RX0_N |
GND | P12 |
| S13 | GND |
CSI1_RX2_P | P13 |
| S14 | CSI0_RX1_P |
CSI1_RX2_N | P14 |
| S15 | CSI0_RX1_N |
GND | P15 |
| S16 | GND |
CSI1_RX3_P | P16 |
| S17 | GBE1_MDIO_P |
CSI1_RX3_N | P17 |
| S18 | GBE1_MDIO_N |
GND | P18 |
| S19 | GBE1_LINK100# |
GBEO_MDI3_N | P19 |
| S20 | GBE1_MDI1_P |
GBEO_MDI3_P | P20 |
| S21 | GBE1_MDI1_N |
GBEO_LINK100# | P21 |
| S22 | - |
GBEO_LINK1000# | P22 |
| S23 | - |
GBEO_MDI2_N | P23 |
| S24 | - |
GBEO_MDI2_P | P24 |
| S25 | GND |
GBEO_LINK_ACT# | P25 |
| S26 | - |
GBEO_MDI1_N | P26 |
| S27 | - |
GBEO_MDI1_P | P27 |
| S28 | USB_VDD33A |
- | P28 |
| S29 | - |
GBEO_MDI0_N | P29 |
| S30 | - |
GBEO_MDI0_P | P30 |
| S31 | GBE1_LINK_ACT# |
- | P31 |
| S32 | - |
GND | P32 |
| S33 | - |
- | P33 |
| S34 | GND |
SDIO_CMD | P34 |
| S35 | USB4_DP |
SDIO_CD# | P35 |
| S36 | USB4_DN |
SDIO_CK | P36 |
| S37 |
|
SDIO_PWR_EN_3V3 | P37 |
| S38 | I2SO_MCK |
GND | P38 |
| S39 | I2S0_LRCK |
SDIO_D0 | P39 |
| S40 | - |
SDIO_D1 | P40 |
| S41 | I2S0_SDIN |
SDIO_D2 | P41 |
| S42 | I2S0_CK |
SDIO_D3 | P42 |
| S43 | - |
SPIO_CS0# | P43 |
| S44 | - |
SPIO_CK | P44 |
| S45 | - |
SPIO_DIN | P45 |
| S46 | - |
SPIO_DO | P46 |
| S47 | GND |
GND | P47 |
| S48 | I2C_GP_CK |
- | P48 |
| S49 |