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Technical introduction SOM-SMARC-QCS5430/6490

Technical introduction SOM-SMARC-QCS5430/6490

Owned by Michael Schieren
yesterday at 14:15
11 min read

Generals

 

 

SOM SMARC QCS-6490_5430_front Kleiner.png

 

Description

QCS6490 and QCS5430 are chipsets that deliver premium features with advanced camera, AI, and compute for high performance at low-power. These chipsets are built for industrial and commercial IoT applications such as ruggedized handhelds and tablets, kiosks, industrial scanners, point of sale systems, human machine interface systems, robotics, drone and controllers, cameras, and edge AI boxes.

SMARC Standard

The SMARC (“Smart Mobility ARChitecture”) is a versatile small form factor computer Module definition targeting applications that require low power, low costs, and high performance. The Modules will typically use ARM SOCs similar or the same as those used in many familiar devices such as tablet computers and smart phones. Alternative low power SOCs and CPUs, such as tablet oriented x86 devices and other RISC CPUs may be used as well.
The Module power envelope is typically under 6W although designs up to about 15W are possible.

 

Blockdiagram

 

image-20250120-152436.png

Features and Interfaces

Features

Processor

Qualcomm QCS Family:

QCS5430 (FP1) (Total 6 cores)

Kryo Gold: 2 x CPU subsystem based on A78 at 2.13 GHz

Kryo Silver: 4 x CPU subsystem based on A55 at 1.8 GHz

QCS5430  (FP2) ( Total 6 cores)

Kryo Prime: 1 x CPU subsystem based on A78 at 2.2 GHz

Kryo Gold: 3 x CPU subsystem based on A78 at 2.13 GHz

Kryo Silver: 4 x CPU subsystem based on A55 at 1.8 GHz

 

QCS6490  (total

Kryo Prime: 1 CPU subsystem based on A78 at 2.7 GHz

Kryo Gold: 3 x CPU subsystem based on A78 at 2.4 GHz

Kryo Silver : 4 x CPU subsystem based on A55 at 1.9 GHz

  • Graphics

    • Integrated Graphics Processing Unit Qualcomm® Adreno™ 642L (QCS5430)

    • Integrated Graphics Processing Unit Qualcomm® Adreno™ 643L(QCS6490)

    • supports 2 independent displays, OpenGL , Open CL , Vulkan.

    Embedded VPU

    • supports H/W decoding of HEVC/H.265, AVC/H.264

    • supports H/W encoding of HEVC/H.265, AVC/H.264

    Video Interfaces

    • LVDS dual channel 18/24 bit, eDP V1.4, MIPI DSI 4 lanes,

    • Display Port through USB 3.1 Type C

    Video Resolution

    • Primary display: FHD+ @120 fps

    • Secondary display: up to 4k Ultra HD @60Hz

Memory

Up to 12GByte of 64-bit LPDDR5-6400

Storage

Up to 64 GByte eMMC

Wireless (optional)

WLAN 802.11 a/b/g/n/ac/ax
BT 5.3
MicroRF-antenna connector

Power

PMIC to generate all internal and external voltages from 3.3V up to 5V supply.

Dimensions

(Length x Width x Height): 82.0 x 50.0 x 5.4 mm

Interfaces / Signals accessible over connector

 

  • Power Supply through 5.0VDC +- 5%, +3.2V_RTC

  • LVDS Dual Channel or eDP (factory alternatives) up to 2560x1600p60

  • HDMI or DP (factory alternatives) up to 4K60

  • SD 4-bit interface (usable as boot device)

  • 2x Gigabit Ethernet interfaces

  • 1x USB 2.0 OTG port

  • 1x USB 3.1

  • up to 4x USB 2.0 using optional internal 2.0 Hub

  • 1x I2S port

  • 2x UART (4-wires)

  • 2x UART (2-wires)

  • 1x CAN interfaces (via SPI CAN Controller)

  • 13x GPIOs

  • 1 x MIPI_CSI0 2 Lanes Camera interface

  • 2 x MIPI_CSI1 4 Lanes Camera Interface

  • 1x General Purpose I2C Bus

  • 2x PWM ports

  • TPM

Technical Documents

1. Pin description

The main connector of the SOM-SMARC- QCS 5430/6490 is the J2800 SMARC connector.
J500 may be used for debugging, programming and testing.

J700 is connection of a third camera.
On the top side are UFL antenna connectors for the on-board WLAN + BT chip.

1.1 Pin description

The following signals are present at the SMARC connector.

Table 1: SMARC connector CN2

Signal

Pin

 

Pin

Signal

Signal

Pin

 

Pin

Signal

 

 

 

S1

I2C6_SCL

SMB_ALERT#

P1

 

S2

I2C6_SDA

GND

P2

 

S3

GND

CSI1_CK_P

P3

 

S4

-

CSI1_CLK_N

P4

 

S5

I2C5_SCL

-

P5

 

S6

-

-

P6

 

S7

I2C5_SDA

CSI1_RX0_P

P7

 

S8

CSI0_CK_P

CSI1_RX0_N

P8

 

S9

CSI0_CK_N

GND

P9

 

S10

GND

CSI1_RX1_P

P10

 

S11

CSI0_RX0_P

CSI1_RX1_N

P11

 

S12

CSI0_RX0_N

GND

P12

 

S13

GND

CSI1_RX2_P

P13

 

S14

CSI0_RX1_P

CSI1_RX2_N

P14

 

S15

CSI0_RX1_N

GND

P15

 

S16

GND

CSI1_RX3_P

P16

 

S17

GBE1_MDIO_P

CSI1_RX3_N

P17

 

S18

GBE1_MDIO_N

GND

P18

 

S19

GBE1_LINK100#

GBEO_MDI3_N

P19

 

S20

GBE1_MDI1_P

GBEO_MDI3_P

P20

 

S21

GBE1_MDI1_N

GBEO_LINK100#

P21

 

S22

-

GBEO_LINK1000#

P22

 

S23

-

GBEO_MDI2_N

P23

 

S24

-

GBEO_MDI2_P

P24

 

S25

GND

GBEO_LINK_ACT#

P25

 

S26

-

GBEO_MDI1_N

P26

 

S27

-

GBEO_MDI1_P

P27

 

S28

USB_VDD33A

-

P28

 

S29

-

GBEO_MDI0_N

P29

 

S30

-

GBEO_MDI0_P

P30

 

S31

GBE1_LINK_ACT#

-

P31

 

S32

-

GND

P32

 

S33

-

-

P33

 

S34

GND

SDIO_CMD

P34

 

S35

USB4_DP

SDIO_CD#

P35

 

S36

USB4_DN

SDIO_CK

P36

 

S37

 

SDIO_PWR_EN_3V3

P37

 

S38

I2SO_MCK

GND

P38

 

S39

I2S0_LRCK

SDIO_D0

P39

 

S40

-

SDIO_D1

P40

 

S41

I2S0_SDIN

SDIO_D2

P41

 

S42

I2S0_CK

SDIO_D3

P42

 

S43

-

SPIO_CS0#

P43

 

S44

-

SPIO_CK

P44

 

S45

-

SPIO_DIN

P45

 

S46

-

SPIO_DO

P46

 

S47

GND

GND

P47

 

S48

I2C_GP_CK

-

P48

 

S49

I2C_GP_DAT

-

P49

 

S50

I2S2_LRCK

GND

P50

 

S51

I2S2_SDOUT

-

P51

 

S52

-

-

P52

 

S53

I2S2_CK

GND

P53

 

S54

-

ESPI_CS0#

P54

 

S55

USB5_EN_OC#

-

P55

 

S56

ESPI_IO_2

ESPI_CK

P56

 

S57

ESPI_IO_3

ESPI_IO_1

P57

 

S58

-

ESPI_IO_0

P58

 

S59

USB5_DP

GND

P59

 

S60

USB5_DN

USB0_DP

P60

 

S61

GND

USB0_DN

P61

 

S62

 

USB0_EN_OC#

P62

 

S63

 

USB0_VBUS_DET

P63

 

S64

GND

USB0_OTG_ID

P64

 

S65

 

USB1_DP

P65

 

S66

 

USB1_DN

P66

 

S67

GND

USB1_EN_OC#

P67

 

S68

USB3_DP

GND

P68

 

S69

USB3_DN

USB2_DP

P69

 

S70

GND

USB2_DN

P70

 

S71

USB2_SS_TXP

USB2_EN_OC#

P71

 

S72

USB2_SS_TXN

STM32_RST#

P72

 

S73

GND

-

P73

 

S74

USB2_SS_RXP

USB3_EN_OC#

P74

 

S75

USB2_SS_RXN

 

 

 

 

 

EXT_PCIE_A_RST#

P75

 

S76

-

USB4_EN_OC#

P76

 

S77

-

PCIE_B_CKREQ#

P77

 

S78

-

PCIE_A_CKREQ#_CON

P78

 

S79

-

GND

P79

 

S80

GND

-

P80

 

S81

-

-

P81

 

S82

-

GND

P82

 

S83

GND

REF_CLKP_CARRIER

P83

 

S84

-

REF_CLKN_CARRIER

P84

 

S85

-

GND

P85

 

S86

GND

PCIE_RXP_CARRIER

P86

 

S87

-

PCIE_RXN_CARRIER

P87

 

S88

-

GND

P88

 

S89

GND

PCIE_TXP_CARRIER

P89

 

S90

-

PCIE_TXN_CARRIER

P90

 

S91

-

GND

P91

 

S92

GND

HDMI_D2+

P92

 

S93

DP0_LANE0+

HDMI_D2-

P93

 

S94

DP0_LANE0-

GND

P94

 

S95

DP0_AUX_SEL

HDMI_D1+

P95

 

S96

DP0_LANE1+

HDMI_D1-

P96

 

S97

DP0_LANE1-

GND

P97

 

S98

DP0_HPD_EXT

HDMI_D0+

P98

 

S99

DP0_LANE2+

HDMI_D0-

P99

 

S100

DP0_LANE2-

GND

P100

 

S101

GND

HDMI_CK+

P101

 

S102

DP0_LANE3+

HDMI_CK-

P102

 

S103

DP0_LANE3-

GND

P103

 

S104

 

HDMI_HPD_EXT

P104

 

S105

DP0_AUX+

HDMI_CTRL_CK

P105

 

S106

DP0_AUX-

HDMI_CTRL_DAT

P106

 

S107

LCD1_BKLT_EN

DP1_AUX_SEL

P107

 

S108

LVDS1_EDP_CLK_P

GPIO0/CAM0_PWR#

P108

 

S109

LVDS1_EDP_CLK_N

GPIO1/CAM1_PWR#

P109

 

S110

GND

GPIO2/CAM0_RST#

P110

 

S111

LVDS1_EDP_D0_P

GPIO3/CAM1_RST#

P111

 

S112

LVDS1_EDP_D0_N

GPIO4

P112

 

S113

EDP1_HPD_EXT

GPIO5

P113

 

S114

LVDS1_EDP_D1_P

GPIO6

P114

 

S115

LVDS1_EDP_D1_N

GPIO7

P115

 

S116

LCD1_VDD_EN

GPIO8

P116

 

S117

LVDS1_TX2_P

GPIO9

P117

 

S118

LVDS1_TX2_N

GPIO10

P118

 

S119

GND

GPIO11

P119

 

S120

LVDS1_TX3_P

GND

P120

 

S121

LVDS1_TX3_N

I2C_PM_CK

P121

 

S122

LCD1_BKLT_PWM

I2C_PM_DAT

P122

 

S123

GPIO13

BOOT_SEL0#

P123

 

S124

GND

BOOT_SEL1#

P124

 

S125

LVDS0_TX0_P

BOOT_SEL2#

P125

 

S126

LVDS0_TX0_N

RESET_OUT#

P126

 

S127

LCD0_BKLT_EN

RESET_IN#

P127

 

S128

LVDS0_TX1_P

POWER_BTN#

P128

 

S129

LVDS0_TX1_N

SER0_TX

P129

 

S130

GND

SER0_RX

P130

 

S131

LVDS0_TX2_P

SER0_RTS#

P131

 

S132

LVDS0_TX2_N

SER0_CTS#

P132

 

S133

LCD0_VDD_EN

GND

P133

 

S134

LVDS0_CK_P

SER1_TX

P134

 

S135

LVDS0_CK_N

SER1_RX

P135

 

S136

GND

SER2_TX

P136

 

S137

LVDS0_TX3_P

SER2_RX

P137

 

S138

LVDS0_TX3_N

SER2_RTS#

P138

 

S139

I2C0_SCL

SER2_CTS#

P139

 

S140

I2C0_SDA

SER3_TX

P140

 

S141

LVDS0_BKLT_PWM

SER3_RX

P141

 

S142

GPIO12

GND

P142

 

S143

GND

CAN0_TX

P143

 

S144

EDP0_HPD

CAN0_RX

P144

 

S145

WDT_TIME_OUT#

 

P145

 

S146

EXT_PCIE_WAKE#

 

P146

 

S147

VDD_RTC

5V_SLEEP

P147

 

S148

LID#

5V_SLEEP

P148

 

S149

SLEEP#

5V_SLEEP

P149

 

S150

VIN_PWR_BAD#

5V_SLEEP

P150

 

S151

CHARGING#

5V_SLEEP

P151

 

S152

CHARGER_PRSNT#

5V_SLEEP

P152

 

S153

CARRIER_STBY#

5V_SLEEP

P153

 

S154

CARRIER_PWR_ON

5V_SLEEP

P154

 

S155

FORCE_RECOV#

5V_SLEEP

P155

 

S156

BATLOW#

5V_SLEEP

P156

 

S157

TEST#

 

 

 

S158

GND

 

2. Interfaces

This chapter includes a short description of all interfaces of the WILK. Please consult the processor datasheet for detailed information.

2.1 Power Supply

The SOM-SMARC-QCS can be supplied by a single +5.0V power supply.

Table 4: Power Supply pins

Name

Description

Name

Description

5V_SLEEP

5V power input.

GND

Ground input

VDD_RTC

3V power supply to supply the RTC on the SOM-SMARC-QCS

 

2.3 UART

The SOM-SMARC-QCS 5430/6490 provides 4 Universal Asynchronous Receiver/Transmitter. With a transceiver these signals can be converted to RS232, RS485 or IrDA.

Following UART ports are accessible through the SMARC connector:

Table 7: UART pins

Name

Description

Name

Description

SER0_TX

Serial 0 transmit output

SER0_RX

Serial 0 receive input

SER0_RTS#

Serial 0 request to send output (active low)

SER0_CTS#

Serial 0 clear to send input (active low)

SER1_TX

Serial 1 transmit output

SER1_RX

Serial 1 receive input

SER2_TX

Serial 2 transmit output

SER2_RX

Serial 2 receive input

SER2_RTS#

Serial 2 request to send output (active low)

SER2_CTS#

Serial 2 clear to send input (active low)

SER3_TX

Serial 3 transmit output

SER3_RX

Serial 3 receive input

Baudrate: High-speed TIA/EIA-232-F compatible, up to 1Mbit/s, IrDA-compatible, up to 115.2 Kbit/s

Data-Bits: 7 or 8 bits (RS232) or 9 bit (RS485)

Stop Bits: 1, 2

Parity: None, Even, Odd

Features: Hardware flow control (RTS, CTS)

 

2.4 SPI

The Serial Peripheral Interface is a programmable synchronous serial port, which may be used to connect to a multiple of different peripherals.

Table 8: SPI pins

Name

Description

Name

Description

SPIO_CS0#

SPI 0 slave select

SPI0_CK

SPI 0 clock

SPI0_DIN

SPI 0 data in

SPI0_DO

SPI 0 data out

SPI1_CS0#

SPI 1slave select

SPI1_CK

SPI 1 clock

SPI1_DIN

SPI 1 data in

SPI1_DO

SPI 1 data out

Speed: up to xxx MHz

 

2.6 I2C

The Inter-Integrated Circuit (I2C ) provides functionality of a standard I2C master and slave.

Table 9: I2C pins

Name

Description

 

 

Name

Description

 

 

I2C0_SCL

I2C0 clock

 

 

I2C0_SDA

I2C0 data

 

 

I2C_GP_CK

I2C GP clock

 

 

I2C_GP_DAT

I2C GP data

 

 

I2C_PM_CK

I2C PM clock

 

 

I2C_PM_DAT

I2C PM data

 

 

Speed: Standard mode, up to 100kbit/s
Fast mode, up to 400 kbit/s

Features: Multimaster operation.
I2C Bus specification version 2.1

 

2.7 I2S

The Inter-IC sound interface provides a synchronous audio interface (SAI) and is used to connect to audio codecs.

Table 10: I2S pins

Name

Description

Name

Description

I2S0_LRCK

I2S0 Left & Right Synchronisation Clock

I2S0_SDOUT

I2S0 Digital Audio Output

I2S0_SDIN

I2S0 Digital Audio Input

I2S0_CK

I2S0 Digital Audio Clock

I2S2_LRCK

I2S2 Left & Right Synchronisation Clock

I2S2_SDOUT

I2S2 Digital Audio Output

I2S2_SDIN

I2S2 Digital Audio Input

I2S2_CK

I2S2 Digital Audio Clock

 

2.8 SDIO

The SDIO interface may be used to connect a SD-Card, eMMC or SDIO hardware.

Table 11: SDIO pins

Name

Description

Name

Description

SDIO_WP

SDIO write protect

SDIO_CMD

SDIO command output

SDIO_CD#

SDIO card detect input (active low)

SDIO_CK

SDIO clk output

SDIO_PWR_EN

SDIO Power enable signal

SDIO_D0

SDIO data bit 0

SDIO_D1

SDIO data bit 1

SDIO_D2

SDIO data bit 2

SDIO_D3

SDIO data bit 3

Speed: Card bus clock frequency up to 208 MHz

Features: Conforms to the SD Host Controller Standard Specification version 3.0.

Compatible with the MMC System Specification version 4.2/4.3/4.4/4.41/5.0.
Compatible with the SD Memory Card Specification version 3.0 and supports the Extended Capacity SD Memory Card
Compatible with the SDIO Card Specification version 3.0

 

2.9 USB

In the standard configuration, the SOM-SMARC-QCS offers one USB 3.1 port and one USB 2.0 ports, which are routed to the SMARC connector, as an assembly option, a quad USB hub is possible, so that up to five USB ports ( 1x USB 3.1 and 4 USB 2.0) are possible on the SMARC connector.

Table 12: USB pins

Name

Description

Name

Description

USB0+

USB Port 0 data (positive), USB2.0

USB0-

USB Port 0 data (negative), USB2.0

USB0_EN_OC#

USB Port 0 power enable output and overcurrent input (active low)

USB0_VBUS_DET

USB Port 0 VBUS detection

USB0_OTG_ID

USB Port 0 ID detect

USB1+

USB Port 1 data (positive), USB2.0

USB1-

USB Port 1 data (negative), USB2.0

USB1_EN_OC#

USB Port 1 power enable output and overcurrent input (active low)

USB2+

USB Port 2 data (positive) (optional)

USB2+

USB Port 2 data (negative) (optional)

USB2_EN_OC#

USB Port 2 power enable output and overcurrent input (active low) (optional)

USB2_SSTX+

USB Port 2 super speed transmit (positive), USB3.1

USB2_SSTX-

USB Port 2 super speed transmit (negative), USB3.1

USB2_SSRX+

USB Port 2 super speed receive (positive), USB3.1

USB2_SSRX-

USB Port 2 super speed receive (negative), USB3.1

USB3_D+

USB Port 3 data (positive) (optional), USB2.0

USB3_D-

USB Port 3 data (negative) (optional), USB2.0

USB3_EN_OC#

USB Port 3 power enable output and overcurrent input (active low)

USB4_D+

USB Port 4 data (positive) (optional), USB2.0

USB4_D-

USB Port 4 data (negative) (optional), USB2.0

USB4_EN_OC#

USB Port 4 power enable output and overcurrent input (active low) (optional)

USB5_D+

USB Port 5 data (positive) (optional), USB2.0

USB5_D-

USB Port 5 data (negative) (optional), USB2.0

USB5_EN_OC#

USB Port 5 power enable output and overcurrent input (active low) (optional)

Speed: High-speed 480Mbit/s
Full-speed 12Mbit/s
Low-speed 1.5Mbit/s

 

2.10 Ethernet

The SOM-SMARC-QCS uses two Texas Instruments DP83867CRRGZR Gigabit Ethernet transceivers

Name

Description

Name

Description

GBE0_MDI0_P

ETH port 0 differential pair 0 positive signal

GBE0_MDI0_N

ETH port 0 differential pair 0 negative signal

GBE0_MDI1_P

ETH port 0 differential pair 1 positive signal

GBE0_MDI1_N

ETH port 0 differential pair 1 negative signal

GBE0_MDI2_P

ETH port 0 differential pair 2 positive signal

GBE0_MDI2_N

ETH port 0 differential pair 2 negative signal

GBE0_MDI3_P

ETH port 0 differential pair 3 positive signal

GBE0_MDI3_N

ETH port 0 differential pair 3 negative signal

GBE0_LINK100#

ETH port 0 Link Speed indication LED for GBE0 100Mbps (active low)

GBE0_LINK1000#

ETH port 0 Link Speed indication LED for GBE0 1000Mbps (active low)

GBE0_LINK_ACT#

ETH port 0 Link / Activity Indication LED driven Low on Link (10, 100 or 1000Mbps) Blinks on Activity (active low)

GBE1_MDI0_P

ETH port 1 differential pair 0 positive signal

GBE1_MDI0_N

ETH port 1 differential pair 0 negative signal

GBE1_MDI1_P

ETH port 1 differential pair 1 positive signal

GBE1_MDI1_N

ETH port 1 differential pair 1 negative signal

GBE1_LINK100#

ETH port 1 Link Speed indication LED for GBE0 100Mbps (active low)

GBE1_LINK_ACT#

ETH port 1 Link / Activity Indication LED driven Low on Link (10, 100 or 1000Mbps) Blinks on Activity (active low)

 

2.11 CAN

The SOM-SMARC-QCS 5430/6490 uses an MCP2518 SPI to CAN converter.

Table 14: CAN pins

Name

Description

Name

Description

CAN0_TX

CAN 0 transmit data

CAN0_RX

CAN 0 receive data

 

2.12 Display

2.12.1 LVDS display or eDP (optional)

Table 15: LVDS or eDP pins

Name

Description

Name

Description

LVDS0_EDP0_TX0+

LVDS port 0 differential pair 0 positive signal

or eDP port differential pair 0 positive signal

LVDS0_EDP0_TX0-

LVDS port 0 differential pair 0 negative signal

or eDP port differential pair 0 negative signal

LVDS0_EDP0_TX1+

LVDS port 0 differential pair 1 positive signal

or eDP port differential pair 1 positive signal

LVDS0_EDP0_TX1-

LVDS port 0 differential pair 1 negative signal

or eDP port differential pair 1 negative signal

LVDS0_EDP0_TX2+

LVDS port 0 differential pair 2 positive signal

or eDP port differential pair 2 positive signal

LVDS0_EDP0_TX2-

LVDS port 0 differential pair 2 negative signal

or eDP port differential pair 2 negative signal

LVDS0_EDP0_TX3+

LVDS port 0 differential pair 3 positive signal

or eDP port differential pair 3 positive signal

LVDS0_EDP0_TX3-

LVDS port 0 differential pair 3 negative signal

or eDP port differential pair 3 negative signal

LVDS0_CK_EDP_AUX+

LVDS port 0 differential clock pair positive signal

LVDS0_CK_EDP_AUX-

LVDS port 0 differential clock pair negative signal

LCD0_BKLT_EN

Backlight enable signal port 0

LCD0_BKLT_PWM

Backlight PWM signal port 0

LCD0_VDD_EN

Power control signal port 0

2.12.2 LVDS

Table 16: LVDS

Name

Description

Name

Description

LVDS1_EDP_D0+

LVDS port 1 differential pair 0 positive signal

LVDS1_EDP_D0-

LVDS port 1 differential pair 0 negative signal

LVDS1_EDP_D1+

LVDS port 1 differential pair 1 positive signal

LVDS1_EDP_D1-

LVDS port 1 differential pair 1 negative signal

LVDS1_EDP_D2+

LVDS port 1 differential pair 2 positive signal

LVDS1_EDP_D2-

LVDS port 1 differential pair 2 negative signal

LVDS1_EDP_D3+

LVDS port 1 differential pair 3 positive signal

LVDS1_EDP_D3-

LVDS port 1 differential pair 3 negative signal

LVDS1_EDP_CLK+

LVDS port 1 differential clock pair positive signal

LVDS1_EDP_CLK-

LVDS port 1 differential clock pair negative signal

LCD1_BKLT_EN

Backlight enable signal

LCD1_BKLT_PWM

Backlight PWM signal

LCD1_VDD_EN

Power control signal

 

 

 

 2.13 Recommended Operating Conditions

 

Pin

Min

Typ

Max

Unit

 

Pin

Min

Typ

Max

Unit

 

Pin

Min

Typ

Max

Unit

 

Pin

Min

Typ

Max

Unit

Supply Voltage

5V_SLEEP

4.75

5.0

5.25

V

 

VDD_RTC

2.0

3.0

3.25

V

Supply current (typ.)
Power consumption dramatically depends on the usage scenario. This includes things like if the processors operqaating point (ffrequency) can be set to a lower level; if the GPU can be used by an application; the selected display resolution

@ 5V_SLEEP

Idle

Using/Running

Typ. Peak currents when running

 

 

 

 

 

 

tbd

tbd

tbd

 

 

 

mA

mA

A

Operating temperature
The chip temperature of processor or LPDDR5 might get hotter. The max. case temperature of QCS is specified with xxx (commercial) and xxx (industrial).

TCommercial

 

TIndustrial

0

 

-30

+25

 

+25

+60

 

+85

°C

 

°C