PI:

Power Input

DO:

Digital Output

PO:

Power Output

DIO:

Digital Input/Output

DDI:

Differential Input

AI:

Analog Input

DDO:

Differential Output

AO:

Analog Output

DDIO:

Differential Input/Output

DI:

Digital Input

OD

Open-Drain Output

PD:

Pull-Down

(PDp: Pull-Down, Pull-behavior can be changed by software)

PU:

Pull-Up

PUp: Pull-Up, Pull-behavior can be changed by software

5V_SLEEP

5V power input. This supply controls the STM32. STM32 MCU controls reset and power to the i.MX 93 processor.

GND

Ground input

VDD_RTC

3V power supply to supply the RTC on the Maury

RESET_IN#

Negated reset input. 0: reset device, 1: normal operation

RESET_OUT#

Negated reset output. 0: device in reset, 1: normal operation (active low)

BOOT_SEL[2…0]

tell the module what physical device to do a BCT boot from (see table xxx below)

STM32_RST#

Negated reset input for STM32. 0: reset STM32, 1: normal operation (active low)

POWER_BTN#

Carrier based power button (active low)

WDT_TIME_OUT#

Watchdog output (active low)

LID#

Lid open/close indication input (active low)

SLEEP#

Sleep indicator input (active low)

VIN_PWR_BAD#

Power status input. 0: Carrierrboard power is not ready to support Maury, 1: Carrierboard power is ready to support Maury (active low)

CHARGING#

Input, held low by carrier during battery scharging, float when charging is complete (active low)

CHARGER_PRSNT#

Input, held low by Carrier if DC input for battery charger is present (active low)

CARRIER_STBY#

Power status output. If the power save state standby
mode is implemented at the Carrier the runtime voltage rails are enabled with this control signal from the module. The module drives this signal high to enable runtime power rails. If no separate standby mode is implemented all rails are enabled with CARRIER_PWR_ON signal. This signal is driven high by the module at runtime. (active low)

CARRIER_PWR_ON

Power status output. It is a signal to Carrier that the
Carrier specific power supplies that shall be powered during standby may be enabled. If standby power save state is implemented at the Carrier this signal enables the standby voltage rails.

FORCE_RECOV#

Primary boot media can be re-initialized (active low)

BATLOW#

Input, battery low indication to Module. Carrier to float the line in inactive state (active low)

TEST#

Negated test input of STM32. 0: device in programming mode, 1: normal operation (active low)

GND

GND

GND

Carrier SATA

GND

GND

Float

Carrier SD Card

GND

Float

GND

Carrier eSPI

GND

Float

Float

Carrier SPI

Float

GND

GND

Module device (NAND, NOR)

Float

GND

Float

Remote boot (GBE, serial)

Float

Float

GND

Module eMMC Flash

Float

Float

Float

Module SPI

SER0_TX

Serial 0 transmit output

SER0_RX

Serial 0 receive input

SER0_RTS#

Serial 0 request to send output (active low)

SER0_CTS#

Serial 0 clear to send input (active low)

SER1_TX

Serial 1 transmit output

SER1_RX

Serial 1 receive input

SER2_TX

Serial 2 transmit output

SER2_RX

Serial 2 receive input

SER2_RTS#

Serial 2 request to send output (active low)

SER2_CTS#

Serial 2 clear to send input (active low)

SER3_TX

Serial 3 transmit output

SER3_RX

Serial 3 receive input

SPIO_CS0#

SPI 0 slave select

SPI0_CK

SPI 0 clock

SPI0_DIN

SPI 0 data in

SPI0_DO

SPI 0 data out

I2C1_SCL

I2C1 clock

I2C1_SDA

I2C1 data

I2C3_SCL

I2C3 clock

I2C3_SDA

I2C3 data

I2C_PM_CK

I2C PM clock

I2C_PM_DAT

I2C PM data

I2S0_LRCK

I2S0 Left & Right Synchronisation Clock

I2S0_SDOUT

I2S0 Digital Audio Output

I2S0_SDIN

I2S0 Digital Audio Input

I2S0_CK

I2S0 Digital Audio Clock

I2S2_LRCK

I2S2 Left & Right Synchronisation Clock

I2S2_SDOUT

I2S2 Digital Audio Output

I2S2_SDIN

I2S2 Digital Audio Input

I2S2_CK

I2S2 Digital Audio Clock

SDIO_CMD

SDIO command output

SDIO_CD#

SDIO card detect input (active low)

SDIO_CK

SDIO clk output

SDIO_PWR_EN_3V3

SDIO Power enable signal

SDIO_D0

SDIO data bit 0

SDIO_D1

SDIO data bit 1

SDIO_D2

SDIO data bit 2

SDIO_D3

SDIO data bit 3

USB0_DP

USB0 data (positive)

USB0_DN

USB0 data (negative)

USB0_EN_OC#

USB0 power enable output and overcurrent input (active low)

USB0_VBUS_DET

USB0 VBUS detection

USB0_OTG_ID

USB0 ID detect

USB1_EXT_DP

USB1 data (positive)

USB1_EXT_DN

USB1 data (negative)

USB1_EN_OC#

USB1 power enable output and overcurrent input (active low)

USB2_DP

USB2 data (positive) (optional)

USB2_DN

USB2 data (negative) (optional)

USB2_EN_OC#

USB2 power enable output and overcurrent input (active low) (optional)

USB3_DP

USB3 data (positive) (optional)

USB3_DN

USB3 data (negative) (optional)

USB3_EN_OC#

USB3 power enable output and overcurrent input (active low) (optional)

USB4_DP

USB4 data (positive) (optional)

USB4_DN

USB4 data (negative) (optional)

USB4_EN_OC#

USB4 power enable output and overcurrent input (active low) (optional)

GBE0_MDI0_P

ETH port 0 differential pair 0 positive signal

GBE0_MDI0_N

ETH port 0 differential pair 0 negative signal

GBE0_MDI1_P

ETH port 0 differential pair 1 positive signal

GBE0_MDI1_N

ETH port 0 differential pair 1 negative signal

GBE0_MDI2_P

ETH port 0 differential pair 2 positive signal

GBE0_MDI2_N

ETH port 0 differential pair 2 negative signal

GBE0_MDI3_P

ETH port 0 differential pair 3 positive signal

GBE0_MDI3_N

ETH port 0 differential pair 3 negative signal

GBE0_LINK100#

ETH port 0 Link Speed indication LED for GBE0 100Mbps (active low)

GBE0_LINK1000#

ETH port 0 Link Speed indication LED for GBE0 1000Mbps (active low)

GBE0_LINK_ACT#

ETH port 0 Link / Activity Indication LED driven Low on Link (10, 100 or 1000Mbps) Blinks on Activity (active low)

GBE1_MDI0_P

ETH port 1 differential pair 0 positive signal

GBE1_MDI0_N

ETH port 1 differential pair 0 negative signal

GBE1_MDI1_P

ETH port 1 differential pair 1 positive signal

GBE1_MDI1_N

ETH port 1 differential pair 1 negative signal

GBE1_MDI2_P

ETH port 1 differential pair 2 positive signal

GBE1_MDI2_N

ETH port 1 differential pair 2 negative signal

GBE1_MDI3_P

ETH port 1 differential pair 3 positive signal

GBE1_MDI3_N

ETH port 1 differential pair 3 negative signal

GBE1_LINK100#

ETH port 1 Link Speed indication LED for GBE0 100Mbps (active low)

GBE1_LINK1000#

ETH port 1 Link Speed indication LED for GBE0 1000Mbps (active low)

GBE1_LINK_ACT#

ETH port 1 Link / Activity Indication LED driven Low on Link (10, 100 or 1000Mbps) Blinks on Activity (active low)

CAN0_TX

CAN 0 transmit data

CAN0_RX

CAN 0 receive data

CAN1_TX

CAN 1 transmit data

CAN1_RX

CAN 1 receive data

LVDS0_TX0_P

LVDS port differential pair 0 positive signal

LVDS0_TX0_N

LVDS port differential pair 0 negative signal

LVDS0_TX1_P

LVDS port differential pair 1 positive signal

LVDS0_TX1_N

LVDS port differential pair 1 negative signal

LVDS0_TX2_P

LVDS port differential pair 2 positive signal

LVDS0_TX2_N

LVDS port differential pair 2 negative signal

LVDS0_TX3_P

LVDS port differential pair 3 positive signal

LVDS0_TX3_N

LVDS port differential pair 3 negative signal

LVDS0_CK_P

LVDS port differential clock pair positive signal

LVDS0_CK_N

LVDS port differential clock pair negative signal

LCD0_BKLT_EN

Backlight enable signal

LCD0_BKLT_PWM

Backlight PWM signal

LCD0_VDD_EN

Power control signal

EDP_DSI_D0_P

MIPI port differential pair 0 positive signal
EDP port differential pair 0 positive signal (optional)

EDP_DSI_D0_N

MIPI port differential pair 0 negative signal
EDP port differential pair 0 negative signal (optional)

EDP_DSI_D1_P

MIPI port differential pair 1 positive signal
EDP port differential pair 1 positive signal (optional)

EDP_DSI_D1_N

MIPI port differential pair 1 negative signal
EDP port differential pair 1 negative signal (optional)

EDP_DSI_D2_P

MIPI port differential pair 2 positive signal
EDP port differential pair 2 positive signal (optional)

EDP_DSI_D2_N

MIPI port differential pair 2 negative signal
EDP port differential pair 2 negative signal (optional)

EDP_DSI_D3_P

MIPI port differential pair 3 positive signal
EDP port differential pair 3 positive signal (optional)

EDP_DSI_D3_N

MIPI port differential pair 3 negative signal
EDP port differential pair 3 negative signal (optional)

EDP_DSI_CLK_P

MIPI port differential clock pair positive signal
EDP port differential clock pair positive signal (optional)

EDP_DSI_CLK_N

MIPI port differential clock pair negative signal
EDP port differential clock pair negative signal (optional)

LCD1_BKLT_EN

Backlight enable signal

LCD1_BKLT_PWM

Backlight PWM signal

LCD1_VDD_EN

Power control signal

CSIO_CK_P

CSI port differential clock pair positive signal

CSIO_CK_N

CSI port differential clock pair negative signal

CSIO_RX0_P

CSI port differential pair 0 positive signal

CSIO_RX0_N

CSI port differential pair 0 negative signal

CSIO_RX1_P

CSI port differential pair 1 positive signal

CSIO_RX1_N

CSI port differential pair 1 negative signal

GPIO0/CAM0_PWR#

Camera 0 power enable signal (active low)

GPIO1/CAM1_PWR#

Camera 1 power enable signal (active low)

GPIO2/CAM0_RST#

Camera 0 reset signal (active low)

GPIO3/CAM1_RST#

Camera 1 reset signal (active low)

Supply Voltage

5V_SLEEP

-0.3

5.5

V

VDD_RTC

-0.3

3.5

V

Storage Temperature

T_Storage

-40

+85

°C

Supply Voltage

5V_SLEEP

4.75

5.0

5.25

V

VDD_RTC

2.0

3.0

3.25

V

Supply current (typ.)
Power consumption dramatically depends on the usage scenario. This includes things like if the processors operqaating point (ffrequency) can be set to a lower level; if the GPU can be used by an application; the selected display resolution

@ 5V_SLEEP

Idle

Using/Running

Typ. Peak currents when running

tbd

tbd

tbd

mA

mA

A

Operating temperature
The chip temperature of processor or LPDDR4 might get hotter. The max. case temperature of 1.MX 93 is specified with xxx (consumer) and xxx (industrial).
A higher refresh-rate-setting is needed when case temperature of LPDDR4 is expected to rise above xxx .
Temperature of eMMC influence the achievable Data Retention

T_Consumer

T_Extended

T_Industrial

0

-25

-40

+25

+25

+25

+85

+85

+85

°C

°C

°C

V(ESD)
Electrostatic discharge

Human body model (HBM)

Charged-device model (CDM)

+/-1000

+/-250

V

V

V_{IL_1V8}

Low-level input voltage

-0.3

0.3 x V_DD

V

V_{IH_1V8}

High-level input voltage

0.7 x V_DD

VDD + 0.3

V

V_{OL_1V8}

High-level output voltage

0

0.2 x V_DD

V

V_{OH_1V8}

Low-level output voltage

0.8 x V_DD

V_DD

V

R_{P_up}

Pull-Up Resistance

12 (typ 22)

49

kOhm

R_{P_down}

Pull-Down Resistance

13 (typ 23)

48

kOhm

V_{IL_1V8}

Low-level input voltage

-

0.3 x V_DDIO

V

V_{IH_1V8}

High-level input voltage

0.7 x x V_DDIO

-

V

V_{OL_1V8}

High-level output voltage

-

0.4

V

V_{OH_1V8}

Low-level output voltage

V_DDIO - 0.45

-

V

R_{P_up}

Pull-Up Resistance

25 (typ 40)

55

kOhm

R_{P_down}

Pull-Down Resistance

25 (typ 40)

55

kOhm