Address-/Databus

For more information on the address-/databus see the i.MX6 Reference Manual chapter 22: External Interface Module (EIM).

The memory mapping of the bus is specified by the IOMUXC_GPR1 register.
On default our software-BSP will configure EIM_CS0 and EIM_CS1 for each having 64MB of memory space.
The EIM_D[31..16] data-pins can be configured through EIM_CSnGCR1 to be used as D[15..0].

Each EIM_CS can be configured with different configuration ( timing, bus-width, address-shift,…).
A software-access with higher bus-width is split into multiple accesses with the configured bus-width in EIM_CSnGCR1.
i.e. a 16bit access ( unsigned short) is split into two 8bit accesses.
You can not access a 8bit address (address-line A0=1), when the bus is configured for 16bit bus-width.

If EIM_CSnGCR1 is configured to not shift the bus according to its bus-width (AUS=1), than this is only true for the virtual address-lines A[23..1].
When using a 16bit bus-width A[25] will still be shifted to EIM_A[24]; A[24] will not be availlable!
Because of that, decoding EIM_CS1 to CS1 and CS4 using EIM_A25 is not possible when using 16bit bus-width.
Only CS4 (pin 106) will be functional in this mode.
Decoding will work when EIM_CS1 is configured to use a 8bit bus-width.

Note

Trizeps VII V1R1 and V1R2 only used EIM_A25 to decode CS1 or CS4.
Since Trizeps VII V1R3, either EIM_A25 or EIM_A24 can be used to decode CS1 or CS4. (resistor mounting option on module)
On standard Trizeps VII V1R3 and later, EIM_A24 is used.

SOFTWARE

Windows Embedded Compact

You can configure the EIM-bus using the registry: EIM-Bus (Trizeps VII)