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Table of Contents

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Description

The Trizeps VIII Plus is powered by NXP i.MX 8M Plus processor, which is designed to meet the latest market requirements of connected streaming audio/video devices, scanning/imaging devices and various devices demanding high-performance and low-power. It offers a 2.3 TOP/s Neural Processing Unit (NPU) for AI-applications like pattern, object and speech recognition.

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PIN

Name

Alt0

Alt1

Alt2

Alt3

Alt4

Alt5

Alt6

Alt7

2

VIN_AD3

ADC0_SE7
ADC1_SE7
ADC1_DM1

PTE19

SPI0_SIN

UART1_
RTS

I2C0_
SCL

 

SPI0_
SOUT

 

4

VIN_AD2

ADC0_SE6
ADC1_SE1
ADC1_DP1

PTE18
LLWI_P20

SPI0_SOUT

UART1_
CTS

I2C0_
SDA

 

SPI0_
SIN

 

 

6

VIN_AD1

ADC0_DM
ADC0_SE5
ADC1_SE5

PTE17
LLWI_P19

SPI0_SCK

UART1_
RX

FTM_
CLKIN1

 

LPTMR0_
ALT3

 

8

VIN_AD0

ADC0_SE1
ADC0_DP
ADC1_SE0

PTE16

SPI0_PCS0

UART1_
TX

FTM_
CLKIN0

 

FTM_
FLT3

 

14

TSPX

ADC0_SE8
ADC1_SE8

PTB0
LLWU_P5

I2C0_SCL

FTM1_
CH0

 

 

FTM1_
QD_PHA

UART0_
RX

16

TSMX

ADC0_SE9
ADC1_SE9

PTB1

I2C0_SDA

FTM1_
CH1

FTM0_
FLT2

EWM_
IN

FTM1_
QD_PHB

UART0_
TX

18

TSPY

ADC0_SE11
CMP1_IN0

PTC2

SPI0_PCS2

UART1_
CTS

FTM0_
CH1

FTM2_
CH1

 

 

20

TSMY

ADC1_SE4
CMP1_IN4
DAC0_OUT

PTE30

 

FTM0_
CH3

 

FTM_
CLKIN1

 

 

24

SPIN24_
CTS3

 

PTA4
LLWU_P3

 

FTM0_
CH1

FTM4_
FLT0

FTM0_
FLT3

 

NMI_b

26

RESET_IN

 

PTA20

 

 

 

 

 

RESET

97

CAN1_RX

 

PTE25
LLWU_P21

CAN0
_RX

FTM0_
CH1

 

I2C0_
SDA

EWM_
IN

 

99

CAN1_TX

 

PTE24

CAN0
_TX

FTM0_
CH0

 

I2C0_
SCL

EWM_
OUT

 

*) Only MKV11 MCU, not usable with MKV10 MCU.

 ADC_SE          Single-Ended ADC
ADC_DM/P      Differential ADC
LLWU              Wakeup-Sources
EWM               External Watchdog Monitor
FTM                 Flexible Timer Module
FTM_CH          Output Channel
FTM_FLT         Fault
FTM_QD_PH   Quadrature Decoder

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