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Description

The Trizeps VIII Plus is powered by NXP i.MX 8M Plus processor, which is designed to meet the latest market requirements of connected streaming audio/video devices, scanning/imaging devices and various devices demanding high-performance and low-power. It offers a 2.3 TOP/s Neural Processing Unit (NPU) for AI-applications like pattern, object and speech recognition.

The i.MX 8M Plus family of processors features advanced implementation of a quad ARM® Cortex®-A53 core, which operates at speeds of up to 1.8GHz (consumer version) and 1.6GHz (industrial version). A general purpose Cortex®-M7 core processor is for low-power processing. A 32-bit LPDDR4 is used for memory. There are a number of other i.MX 8M Plus interfaces for connecting peripherals, such as displays, cameras, GPS and sensors, which are extended by components already available on the module:

• a stereo, hi-fi quality audio-codec.

• a FPGA with up to 4300 LUT to convert MIPI-DSI to parallel 24bpp display data and for user defined programmable logic.

• a programmable Cortex-M0 Kinetis MCU, capable of realtime processing, reading multiple 16bit analog inputs or usable as resistive touch-controller.

• WLAN 802.11 a/b/g/n/ac and BT 4.2 / 5 module

The Trizeps VIII Plus module got a SODIMM200 card edge connector and a 60pin FX11 high-speed board connector. The pinning of both connectors is to a large extent compatible to previous Trizeps modules.

Difference to Trizeps VIII

The i.MX 8M Plus processor of Trizeps VIII Plus benefits from advanced 14nm LPC FinFET Technology, which allows for lesser power-consumption and higher operating frequencies than the i.MX8 used on Trizeps VIII.

The Trizeps VIII offers:

• support of 4K displays

It misses following features:

• 2.3 TOP/s NPU (Neural Processing Unit)

• 2x CAN

• second Ethernet-MAC

• third SDIO-port routed to SODIMM

Difference to Trizeps VIII Mini

The i.MX 8M Mini processor of Trizeps VIII Mini can be considered as the predecessor to the i.MX 8M Plus processor used on Trizeps VIII Plus.

The Trizeps VIII Mini lacks some of the interfaces:

• 2.3 TOP/s NPU (Neural Processing Unit)

• 2x CAN

• second Ethernet-MAC

• third SDIO-port routed to SODIMM

• HDMI

• multi-display support: only MIPI-DSI or LVDS may be used at the same time.

• only USB2.0, instead of USB3.0 ports.

Block Diagram

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Technical Documents

Manual:

• Trizeps VIII Plus Manual

Changes of key components over the revisions

Features and Interfaces

Features

Processor:

NXP i.MX 8M Plus ARM^® Quad Cortex-A53 at up to 1.8GHz (consumer), 1.6GHz (industrial)
NXP i.MX 8M Plus ARM^® Cortex-M7 at up to 800MHz
Neural Processing Unit 2.3 TOPS
NXP Kinetis V ARM^® Cortex-M0+ at up to 75MHz

Memory:

Up to 8 GByte of 32-bit LPDDR4-4000

Storage:

Micro-SD socket or
4 or 8 GByte eMMC
Higher densities are available on request.

Wireless:

WLAN 802.11 a/b/g/n/ac
BT 4.2 and BT 5.0
Micro RF-antenna connector

Power:

PMIC to generate all internal and external voltages from VSYS supply.

Dimensions:

(Length x Width x Height):      67.6 x 36.7 x 6.4 mm

Interfaces / Signals accessible over connectors

• Power Supply from +3.3V to +5V

• 2x USB3.0 OTG port (USB Host or Slave)

• PCIe

• 2x SD/SDIO Card Interface

• 4x UART

• SPI and Quad-SPI

• 2x I2C

• MIPI Display (4ch) or parallel RGB Display

• Single/Dual LVDS

• HDMI

• 2x Mipi Camera (4ch)

• 1000/100/10Mbit Ethernet

• 2x CAN/CAN-FD

• 2x 4ch 16bit ADC

• Stereo Headphone

• Stereo Line-In

• Microphone input (mono, optional stereo)

• 1W Speaker output

• SPDIF In and Out

• Multi-Channel Serial-Audio-Interface

• GPIO, PWM

1      Pin-description

The main connector of the Trizeps VIII Plus is the SODIMM200 connector.
To operate, only VSYS and GND pins need to be connected. Leave unused pins unconnected.
The U14 Board2Board connector can be omitted if the signals are not needed.
J1 and J2 may be used for debugging, programming and testing.
On the bottom side are UFL antenna connectors for the on-board WLAN + BT- chip.

1.1      Pin-description (Primary Function)

The i.MX8M Plus processor, the Cortex M0+ MCU and the FPGA are highly configurable devices, where each pin may have multiple different functions.
The pin-names are derived from previous Trizeps-versions and their primary or most interesting function.
Please view chapter “1.2 Pin-Mux Information” for details on how these pins may be configured by software.

Notes:

*1) In the table below, some of the old Trizeps pin-names are placed in brackets [] for reference.

*2) FPGA_CIF_D[9..0]  / SAIx_RXD[7..0], FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are routed to the FPGA and the i.MX 8M Plus. In the following documentation they are either named FPGA_CIF_Dx or SAIx_RXDy, depending if the FPGA or i.MX 8M Plus function is described.

*3) FPGA_CIF_VSYNC, FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are connected to i.MX 8M Plus pins, if the FPGA is not mounted (RA72).

*4) BT_PCM_IN, BT_PCM_OUT, BT_PCM_SYNC and BT_PCM_CLK are connected to the on-board BT-module if it is mounted!

*5) PCIE_CLKREQ may not be usable when Wifi module is mounted.

J1: SODIMM Connector