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Depending on the configuration and following revisions, the features of the board are subject to change. For detailed information on hardware specifications, please visit www.seco.com |
SBC-pITX-Titan 290 EHL is a PicoITX compliant module with the Intel® Atom® x6000E Series and Intel® Pentium® and Celeron® N and J Series processors. Designed and optimized for Functional Safety (FuSa) applications, this module offers flexibility, reliability, and safety for a wide range of applications across multiple industries.
For ordering purposes, the SBC-pITX-Titan 290 EHL is referred to by its base code, “D63”“SYS-D63-IPC”.
INDEX
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How can I use GPIO/I2C/SPI peripherals?
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Please refer to the following instructions to prevent damage! |
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Peripheral | BIOS setup option to enable peripheral |
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Chipset SPI1 | Chipset → PCH-IO Configuration → PSE Configuration → SPI1 → Host owned with pin muxed |
Chipset SPI3 | Chipset → PCH-IO Configuration → PSE Configuration → SPI3 → Host owned with pin muxed |
MEC SPI | It is enabled automatically when first transmission request is done. Disable Chipset SPI3 before use it! |
QEP0 | Chipset → PCH-IO Configuration → PSE Configuration → QEP0 → Host owned with pin muxed |
QEP1 | Chipset → PCH-IO Configuration → PSE Configuration → QEP1 → Host owned with pin muxed |
PWM1 (Chipset PWM06) | Chipset → PCH-IO Configuration → PSE Configuration → PWM Pin Mux Selection → PWM6 → Enabled |
PWM2 (Chipset PWM02) | Chipset → PCH-IO Configuration → PSE Configuration → PWM Pin Mux Selection → PWM2 → Enabled |
Chipset I2C0 | Chipset → PCH-IO Configuration → SerialIo Configuration → I2C3 Controller → Enabled |
MEC I2C0 | It is enabled automatically when first transmission request is done. Disable Chipset I2C0 before use it! |
Chipset I2C1 | Chipset → PCH-IO Configuration → SerialIo Configuration → I2C1 Controller → Enabled |
MEC I2C1 | It is enabled automatically when first transmission request is done. Disable Chipset I2C1 before use it! |
GPIO 0-7 (MEC) | Advanced → Embedded Controller → GPIO Configurations → Configuration → <Select desired default> |
GPIO 0-7 (Chipset) | Disable conflicting functions if you want to use the pin as GPIO. GPIO pins can’t be used both from MEC and Chipset. MEC GPIO Pins has to be set as Input if you want to use Chipset GPIO pins |
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What is loaded in a standard module?
Off-the-shelf products are shipped with a standard in-house-developed software.
The definition of standard, in this case, is “the environment which SECO adopts for validation”.
Anyway, custom in-house-developedsoftware with different defaults can be built in accordance with customers' requirements submitting a new ticket.
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Other available BIOS versions: |
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Updating the BIOS
https://secogroup.atlassian.net/l/c/6PB1jhmQ
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Further Reading
Visit our Blog to find some tips!
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Downloads
Here you can find the latest version available:
BIOS | |
BIOS Tools | |
Driver WIN10 LTSC | seco_elkhartlake_driver_windows10-2021-ltsc_mr5-rs5-1.00.00.7z |
Driver WIN11 24H2 LTSC | |
Connectivity Driver | seco_elkhartlake_Connectivitydriver_windows10-2021-ltsc_1.00.00.7z |
6.x.x Linux Kernel | |
EAPI |
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Clea OS
This board is fully supported by Edgehog Clea OS, the operating system for the All-In-One IIot CLEA platform developed by SECO and based on Yocto. Edgehog Clea OS is intended to provide the highest standards in terms of security and stability through features such as OTA (Over the Air) updates, dual partitions and fallback procedures. Edgehog Clea OS integrates a Device Manager to communicate with the Cloud and allows a family of products to be managed as a fleet.
Source code
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The source code of Edgehog OS is available at the following link.
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for Clea OS can be found at the following Gitlab organization. To build a complete Yocto image from source, you can follow the readme of the repo manifest.
Binaries
The Yocto image binaries associated with the various versions of Edgehog OS are available Clea OS releases can be found at the following link Release page.