Skip to end of banner Go to start of banner

JTAG CPLD programming

Skip to end of metadata

Created by Anu Selvaraj, last modified on 14. Oct 2022

Go to start of metadata

You are viewing an old version of this page. View the current version.

Compare with Current View Page History

The following pictures show the pin assignment for programming Xilinx respectively Lattice CPLD's using Keith & Koep's JTAG debug PCB.

Xilinx CPLD

Lattice CPLD

No labels