Trizeps6 CPLD

This page explains the default-functionality of the Trizeps6 CPLD.
Keith & Koep can deliver Trizeps6 with customized CPLD-content. In example if not needed, the 26 address-pins of the Trizeps6 may be used as GPIO or one of the UART's can be multiplexed to allow even more serial-ports.

Currently there are two basic CPLD-versions:

1. for Trizeps6 with WLAN/BT ( 26060 and 26080)

2. for Trizeps6 without WLAN/BT ( 26020 and 26040)

The main difference between these modules is, that the ones with WLAN/BT only have an 8Bit multiplexed Address/Databus.

Default functions:

• Decode the multiplexed Address-/Databus to form 4 ChipSelects with 64MB of address-space each.

• Power-Management of the module.

• Control special-functions like GPIO and PWM.

Address-Mapping

The CPLD is connected to CS0 of the processor (0x80000000 physical-address).

Modules without WLAN/BT

For modules without WLAN/BT, you simply do an 16bit data-access with the given offset:

volatile short *padr = (volatile short*)PLATFORM_BASE_VA_CS3;
*padr = 123;

Modules with WLAN/BT

For modules which use D[15..8] for WLAN, Keith & Koep offers 2 options:

1. Reduced Address-Space (default)

Because D[15..8] are latched to create the A[31..24] and A[15..8] address-lines and are not availlable on modules which use them for WLAN, the CPLD only decodes a reduced address space and shifts A[23..16] by four bits to the left.

With this configuration it is still possible to access 8192 addresses (A[0] unused).

#define PLATFORM_BASE_PA_CSX     0x80000000
#define A20                      (1<<16)
#define A21                      (1<<17)
#define A22                      (1<<18)
#define A23                      (1<<19)
#define A24                      (1<<20)
#define A25                      (1<<21)
#define A26                      (1<<22)
#define A27                      (1<<23)
#define OFFSET_CS3                A27
#define CUSTOM_REG_CS3_A22_PA   ((UNSIGNED LONG) PLATFORM_BASE_PA_CSX+OFFSET_CS3+A22)            

// Write to Custom Reg on CS3 with A22 set.
(*volatile short *)CUSTOM_REG_CS3_A22_PA=0x1234;  

2. Whole Address-Space

To be able to use the whole address-space on modules which use D[15..8] for WLAN, you must do two successive reads/writes. Read/Writes to the internal CPLD-registers only need one access!! The address of the first read specifies address-lines 27..24 and 7..0.
The second read/write specifies the address-lines 23..16 and 15..0.

o == don't care.
Data of the first access is ignored!
Write-Example:

    volatile short *padr;
    padr = (volatile short*)( csbase + (offset & 0xFF00FFFF) + ((offset>>8)&0x00FF0000));
    *padr = 0; // dummy write to latch A[27..24] and A[7..0];
    padr = (volatile short*)( csbase + (offset & 0xFFFFFF00) + ((offset>>8)&0x000000FF)); 
    *padr = value; // latch A[23..16], A[15..8] and write value to address;

When using Windows Embedded CE, you may use following drvlib_app-functions: DFIOMapSpace , DFIOWrite, DFIORead.

CPLD-Registers

s/c:
0 - set specified bits.
1 - clear specified bits.
-: don't care.

REG_CONTROL (0xbf7e0000, 0xbf7e0002)

read: Reading this register returns the CPLD-Version.

REG_FEATURE (0xbf7e0004, 0xbf7e0006)

REG_HIBERNATE (0xbf7e0008, 0xbf7e000a )

REG_PWM (0xbf7e000c)

D[6..0] PWM-Match-value.

REG_PINLDR (0xbf7e0010, 0xbf7e0012)

read: read level of pin.
write: write direction of pin. 1:output, 0:input.

REG_PINSET (0xbf7e0014, 0xbf7e0016)

read: -.
write: write level of pin.

REG_TTLIO (0xbf7e0018, 0xbf7e001a)

Uses address pins as input and output-pins, when USE_TTLIO is set in REG_FEATURE.

read: read level of pin.
write: write level of pin.

See Also

CPLDAction,
DFIOMapSpace,
DFIORead,
DFIOWrite