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This page explains the default-functionality of the Trizeps6 CPLD.
Keith & Koep can deliver Trizeps6 with customized CPLD-content. In example if not needed, the 26 address-pins of the Trizeps6 may be used as GPIO or one of the UART's can be multiplexed to allow even more serial-ports.

Currently there are two basic CPLD-versions:

  1. for Trizeps6 with WLAN/Bluetooth ( 26060 and 26080)

  2. for Trizeps6 without WLAN/Bluetooth ( 26020 and 26040)

The main difference between these modules is, that the ones with WLAN/Bluetooth only have an 8Bit multiplexed Address/Databus.

Default functions:

  • Decode the multiplexed Address-/Databus to form 4 ChipSelects with 64MB of address-space each.

  • Power-Management of the module.

  • Control special-functions like GPIO and PWM.

Address-Mapping

The CPLD is connected to CS0 of the processor (0x80000000 physical-address).

A27

A26

A25

Offset

Description

0

0

-

0x00000000

CS 64MB ( reserved for future use)

0

1

-

0x04000000

CS1 64MB

1

0

-

0x08000000

CS3 64MB

1

1

0

0x0C000000

CS4 32MB

1

1

1

0x0E000000

CPLD-Registers

Modules without WLAN/BT

For modules without WLAN/BT, you simply do an 16bit data-access with the given offset:

volatile short *padr = (volatile short*)PLATFORM_BASE_VA_CS3;
*padr = 123;

Modules with WLAN/BT

For modules which use D[15..8] for WLAN, Keith & Koep offers 2 options:

1. Reduced Address-Space (default)

Because D[15..8] are latched to create the A[31..24] and A[15..8] address-lines and are not availlable on modules which use them for WLAN, the CPLD only decodes a reduced address space and shifts A[23..16] by four bits to the left.

Access

Address

Description

1

0xooaaoobb

a: Address 27..20; bb: Address 7..0 → 0x0aa000bb

With this configuration it is still possible to access 8192 addresses (A[0] unused).

#define PLATFORM_BASE_PA_CSX     0x80000000
#define A20                      (1<<16)
#define A21                      (1<<17)
#define A22                      (1<<18)
#define A23                      (1<<19)
#define A24                      (1<<20)
#define A25                      (1<<21)
#define A26                      (1<<22)
#define A27                      (1<<23)
#define OFFSET_CS3                A27
#define CUSTOM_REG_CS3_A22_PA   ((UNSIGNED LONG) PLATFORM_BASE_PA_CSX+OFFSET_CS3+A22)            

// Write to Custom Reg on CS3 with A22 set.
(*volatile short *)CUSTOM_REG_CS3_A22_PA=0x1234;  
2. Whole Address-Space

To be able to use the whole address-space on modules which use D[15..8] for WLAN, you must do two successive reads/writes. Read/Writes to the internal CPLD-registers only need one access!! The address of the first read specifies address-lines 27..24 and 7..0.
The second read/write specifies the address-lines 23..16 and 15..0.

Access

Address

Description

1

0xoooaoobb

a: Address 27..24; bb: Address 7..0

2

0xooccoodd

cc: Address 23..16; dd: Address 15..8

o == don't care.
Data of the first access is ignored!
Write-Example:

    volatile short *padr;
    padr = (volatile short*)( csbase + (offset & 0xFF00FFFF) + ((offset>>8)&0x00FF0000));
    *padr = 0; // dummy write to latch A[27..24] and A[7..0];
    padr = (volatile short*)( csbase + (offset & 0xFFFFFF00) + ((offset>>8)&0x000000FF)); 
    *padr = value; // latch A[23..16], A[15..8] and write value to address;

When using Windows Embedded CE, you may use following drvlib_app-functions: DFIOMapSpace , DFIOWrite, DFIORead.

CPLD-Registers

A4

A3

A2

A1

Offset

Description

Write

Read

Virtual Bootloader-Address

0

0

0

s/c

0x0000

REG_CONTROL

Control/Reset

Module Version

0xbf7e0000, 0xbf7e0002

0

0

1

s/c

0x0004

REG_FEATURE

Features/Pin-Routing

Feature, PCB-Version

0xbf7e0004, 0xbf7e0006

0

1

0

s/c

0x0008

REG_HIBERNATE

Hibernate/Wake-Control

-

0xbf7e0008, 0xbf7e000a

0

1

1

-

0x000c

REG_PWM

PWM(6..0)

-

0xbf7e000c

1

0

0

s/c

0x0010

REG_PINLDR

Pin-Direction

Pin-Level

0xbf7e0010, 0xbf7e0012

1

0

1

s/c

0x0014

REG_PINSET

Pin-Level

-

0xbf7e0014, 0xbf7e0016

1

1

0

s/c

0x0018

REG_TTLIO

TTL-Output-Port

TTL-Input-Port

0xbf7e0018, 0xbf7e001a

s/c:
0 - set specified bits.
1 - clear specified bits.
-: don't care.

REG_CONTROL (0xbf7e0000, 0xbf7e0002)

Bit

Description

0

-

1

-

2

Reset Audio/Touch Codec

3

Reset Ethernet-Phy

4

Reset WLAN

5

Reset Bluetooth

6

-

7

-

read: Reading this register returns the CPLD-Version.

REG_FEATURE (0xbf7e0004, 0xbf7e0006)

Write

Bit

Description

0

Route UART3 to SODIMM

1

Route UART3 to Bluetooth

2

CompactFlash-mode (disable UART3)

3

Use TTLIO (see description of TTLIO-register)

4

Output PWM on SODIMM-Pin 69

5

Output PWM on SODIMM-Pin 77

6

Output PWM on SODIMM-Pin 106

7

Route Bluetooth-PCM to SODIMM ( 188(A16): PCM_SYNC, 186(A17): PCM_CLK, 184(A18): PCM_OUT, 146(A19): PCM_IN)

Read

Bit

Description

0

0: Use Whole Address-Space (16Bit DFIO), 1: Use Reduced Address-Space (8Bit DFIO).

1

-

2

-

3

-

7..4

Trizeps VI PCB Revision

REG_HIBERNATE (0xbf7e0008, 0xbf7e000a )

Bit

Description

0

Enter Hibernate Mode

1

Wake on Touch

2

Wake on EXT_WAKEUP (PMIC)

3

Wake on IRQ=High (SODIMM-Pin 43)

4

Wake on Reset (CPLD Ver >= 4)

5

Wake on IRQ=Low (SODIMM-Pin43)(CPLD Version >= 7)

6

-

7

-

REG_PWM (0xbf7e000c)

D[6..0] PWM-Match-value.

REG_PINLDR (0xbf7e0010, 0xbf7e0012)

Bit

Description

Use with this GPIO-number in GPIO-functions

0

SODIMM-Pin 69

127

1

SODIMM-Pin 100 (PSKTSEL)

126

2

SODIMM-Pin 98 (CF_nREG)

125

3

SODIMM-Pin 104 (CF_nIOIS16)

124

4

SODIMM-Pin 93 (RDnWR)

130

5

Route CF_nIOIS16 (SODIMM-Pin 104) to IRQ (SODIMM-Pin 43)

-

6

-

-

7

-

-

read: read level of pin.
write: write direction of pin. 1:output, 0:input.

REG_PINSET (0xbf7e0014, 0xbf7e0016)

Bit

Description

Use with this GPIO-number in GPIO-functions

0

SODIMM-Pin 69

127

1

SODIMM-Pin 100 (PSKTSEL)

126

2

SODIMM-Pin 98 (CF_nREG)

125

3

SODIMM-Pin 104 (CF_nIOIS16)

124

4

SODIMM-Pin 93 (RDnWR)

130

5

-

-

6

-

-

7

-

-

read: -.
write: write level of pin.

REG_TTLIO (0xbf7e0018, 0xbf7e001a)

Uses address pins as input and output-pins, when USE_TTLIO is set in REG_FEATURE.

Bit

Description

Write

Read

0

A8

A0

1

A9

A1

2

A10

A2

3

A11

A3

4

A12

A4

5

A13

A5

6

A14

A6

7

A15

A7

read: read level of pin.
write: write level of pin.

See Also

CPLDAction,
DFIOMapSpace,
DFIORead,
DFIOWrite

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