STM32 MCU - QCS5430
Customers may request access to the source-code of the firmware to modify it for their needs.
Commands & Registers (I2C)
I2C-Address: 0x40 (7-bit) | ||||
Register | Name | Access | Description | Default Value |
0x01 | REG_ID | read | ID-Register | 0x49 |
0x02 | REG_CONTROL | write | Restart and boot with BOOT_MODE= 0x04 - Shutdown (Hard) | - |
0x03 | REG_CONFIG | - | - | - |
0x04 | REG_PIN_CONFIG | write | <Pin> <Parameter> 0x01: Input, NoPull 0x20: Output PushPull, init low level 0x80: IRQ Rising Edge | - |
0x05 | REG_PIN_SET | write | <Pin> <Level> | - |
0x06 | REG_PIN_GET | write | <Pin> | - |
0x07 | REG_PWM_CONFIG | write | <Pin> <Duty Cycle [%]> | - |
0x08 | REG_ALTERNATE_ | write | Set Pin to specific alternate function. <Pin> <Alternate Function> Alternate Functions: |
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0x09 | REG_ADC_READ | read | Read ADC Value 0x01: EXT_DCIN_PG | - |
0x0A | REG_INT_STATUS0 | read | Read INT_STATUS1 register, clear it and reset EC_IRQ#_OD to “1” if all interrupts are read. 0x01: GPIO4 | 0x00 |
0x0B | REG_INT_ENABLE0 | r/w | Enable interrupts. Same signals as in REG_INT_STATUS1. | 0x00 |
0x0C | REG_INT_STATUS1 | read | Read INT_STATUS2 register, clear it and reset EC_IRQ#_OD to “1” if all interrupts are read. | 0x00 |
0x0D | REG_INT_ENABLE1 | r/w | Enable interrupts. Same signals as in REG_INT_STATUS2. | 0x00 |
0x0E | REG_INT_STATUS2 | read | Read INT_STATUS3 register, clear it and reset EC_IRQ#_OD to “1” if all interrupts are read. | 0x00 |
0x0F | REG_INT_ENABLE2 | r/w | Enable interrupts. Same signals as in REG_INT_STATUS3. | 0x00 |
0x80 | REG_SECO_CODE | - | - |
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0x90 | REG_RAM_CODE | - | - |
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0xF0 | REG_VERSION | read | Read firmware version | 0x01 |
Configurable GPIO Pins (I2C)
The following Pins are configurable via I2C:
Pin# | Name | Default Configuration | IRQ | Alternate Function |
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0 | GPIO4 | Input, NoPull |
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1 | GPIO5 | Input, NoPull | PWM | |
2 | GPIO6 | Input, NoPull |
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3 | GPIO7 | Input, NoPull |
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4 | GPIO8 | Input, NoPull |
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5 | GPIO9 | Input, NoPull |
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6 | GPIO12 | Input, NoPull |
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7 | GPIO13 | Input, NoPull | * |
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8 | BT_IRQ | (only usable as IRQ source) |
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9 | RTC_INT# | (only usable as IRQ source) |
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10 | SMB_ALERT# | (only usable as IRQ source) |
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11 | USB0_EN_OC# | Output, OpenDrain, init low level | * |
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12 | USB1_EN_OC# | Output, OpenDrain, init low level |
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13 | USB2_EN_OC# | Output, OpenDrain, init low level |
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14 | USB3_EN_OC# | Output, OpenDrain, init low level |
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15 | USB4_EN_OC# | Output, OpenDrain, init low level | * |
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16 | CPU_IRQ# | Input, NoPull |
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17 | LID# | Input, NoPull |
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18 | BATLOW# | Input, NoPull |
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19 | USB0_OTG_ID | Input, NoPull |
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20 | RESET_OUT# | Output, PushPull, init low level, set high ~100ms after startup (-> SMARC Spec.) |
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21 | SDIO_PWR_EN | Output, PushPull, init high level |
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22 | USB0_VBUS_DET | Input, NoPull |
| !!!! ggf an PM7325 GPIO_09 !!!! |
23 | WIFI_DISABLE | Output, PushPull, init high level |
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24 | LCD0_VDD_EN | Output, PushPull, init low level |
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25 | CHARGER_PRSNT# | Input, NoPull |
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26 | CHARGING# | Input, NoPull |
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27 | ENET_SDP_TRANSL_EN | Input, NoPull |
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28 | WIFI_PWRDWN# | Output, PushPull, init low level |
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29 | USB_HUB_RST# | Output, PushPull, init low level |
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*: Polled IRQ
Carrier board BOOT_SEL configuration
The BOOT_SEL[2:0] Configuration on the carrier board is used to determine the boot device by setting FAST_BOOT[2:0]
BOOT_SEL[2:0]# | BOOT_MODE[3:0] | Boot Device |
---|---|---|
0 0 1 | 0 0 1 1 | Carrier SD Card (SD2) |
1 0 0 | 0 0 0 0 | UFS |
1 0 1 | 0 0 0 1 | USB Boot (default) |
1 1 0 | 0 0 1 0 | Module eMMC (SD1) |
Any other BOOT_SEL configuration will be treated like the default option.
Connecting FORCE_RECOV# to GND will cause the STM32 to set FORCED_USB_BOOT to a low signal level to force the system into USB Boot mode.
Other Functions
Holding the RESET button for >= 10 seconds will cause the system to reboot into serial download mode rather than rebooting into the mode selected by the BOOT_SEL configuration of the carrier board.