Generals

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Description

The Wilk is powered by MediaTek Genio 700 or MediaTek Genio 510 Applications Processor. They are designed to meet the latest market requirements of connected streaming audio/video devices, scanning/imaging devices and various devices demanding high-performance and low-power.

The Genio 510 features advanced implementation of a dual ARM® Cortex®-A78 core, which operates at speeds of up to 2.0GHz and four ARM® Cortex®-A55 core, which operates at speeds of up to 2.0GHz

The Genio 700 features advanced implementation of a dual ARM® Cortex®-A78 core, which operates at speeds of up to 2.2GHz and six ARM® Cortex®-A55 core, which operates at speeds of up to 2.0GHz.

An Mali G57 MC3 GPU is also integrated as Cadence Tensilica VP6 with MediaTek APU3.0 for AI Acceleration.

A 64-bit LPDDR4 interface is used for memory. There are a number of other interfaces for connecting peripherals, such as displays, cameras, GPS and sensors, which are extended by components already available on the module:

• eMMC (up to 64 GByte)

• upto 2x 1Gbit Ethernet

• TPM

• 1x USB 3.1 2x USB 2.0

• MIPI/eDP, HDMI/DP

• RTC

• EEPROM

• WLAN 802.11 a/b/g/n/ac and BT 5.3 Combo module (M.2 1216)

SMARC Standard

The SMARC (“Smart Mobility ARChitecture”) is a versatile small form factor computer Module definition targeting applications that require low power, low costs, and high performance. The Modules will typically use ARM SOCs similar or the same as those used in many familiar devices such as tablet computers and smart phones. Alternative low power SOCs and CPUs, such as tablet oriented x86 devices and other RISC CPUs may be used as well.
The Module power envelope is typically under 6W although designs up to about 15W are possible.

Block Diagram

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Features and Interfaces

Features

Processor

MediaTek Genio 700 ARM^® Octa-core CPU (Dual Cortex-A78 @ 2.2 GHz and Six Cortex-A55 @ 2.0 GHz)
MediaTek Genio 510 ARM^® Six-core CPU (Dual Cortex-A78 @ 2.0 GHz and Four Cortex-A55 @ 2.0 GHz)
Mali G57 MC3 GPU
AI Accelerator: Cadence Tensilica VP6 with MediaTek APU3.0
System Companion Chip: MDSP RV55
DSP: Cadence Tensilica HiFi5

Memory

Up to 8GByte of 64-bit LPDDR4-4000

Storage

Up to 64 GByte eMMC

Wireless

WLAN 802.11 a/b/g/n/ac/ax
BT 5.3
MicroRF-antenna connector

Power

PMIC to generate all internal and external voltages from 3.3V up to 5V supply.

Dimensions

(Length x Width x Height): 82.0 x 50.0 x 5.4 mm

Interfaces / Signals accessible over connector

• Power Supply through 5.0VDC +- 5%, +3.2V_RTC

• LVDS Dual Channel or eDP (factory alternatives) up to 2560x1600p60

• HDMI or DP (factory alternatives) up to 4K60

• SD 4-bit interface (boot device)1

• 2x Gigabit Ethernet interfaces

• 1x USB 2.0 OTG port

• up to 4x USB 2.0 using optional internal 2.0 Hub

• 1x I2S port

• 2x UART (4-wires)

• 2x UART (2-wires)

• 1x CAN interfaces (via SPI CAN Controller)

• 13x GPIOs

• 1 x MIPI_CSI0 2 Lanes Camera interface

• 1 x MIPI_CSI1 4 Lanes Camera Interface

• 1x General Purpose I2C Bus

• 2x PWM ports

• TPM

Technical Documents

1. Pin description

The main connector of the WILK is the J2800 SMARC connector.
J500 may be used for debugging, programming and testing.
On the top side are UFL antenna connectors for the on-board WLAN + BT chip.

1.1 Pin description

The following signals are present at the SMARC connector.

Table 1: J2800: SMARC connector