SOM-SMARC-Genio510 / Genio700
- Michael Schieren
- 1.1 Generals
- 1.2 Description
- 1.3 SMARC Standard
- 1.4 Block Diagram
- 2 Features and Interfaces
- 2.1 Features
- 2.1.1 Processor
- 2.1.2 Memory
- 2.1.3 Storage
- 2.1.4 Wireless
- 2.1.5 Power
- 2.1.6 Dimensions
- 2.1.7 Interfaces / Signals accessible over connector
- 2.1 Features
- 3 Technical Documents
- 4 1. Pin description
- 5 2. Interfaces
- 5.1 2.1 Power Supply
- 5.2 2.2 Control signals
- 5.3 2.3 UART
- 5.3.1 Table 7: UART pins
- 5.4 2.4 SPI
- 5.4.1 Table 8: SPI pins
- 5.5 2.5 eSPI
- 5.5.1 Table 8: SPI pins
- 5.6 2.6 I2C
- 5.6.1 Table 9: I2C pins
- 5.7 2.7 I2S
- 5.7.1 Table 10: I2S pins
- 5.8 2.8 SDIO
- 5.8.1 Table 11: SDIO pins
- 5.9 2.9 USB
- 5.9.1 Table 12: USB pins
- 5.10 2.10 Ethernet
- 5.10.1 Table 13: Ethernet pins
- 5.11 2.11 CAN
- 5.11.1 Table 14: CAN pins
- 5.12 2.12 Display
- 5.13 2.12.1 LVDS-display
- 5.13.1 Table 15: LVDS pins
- 5.14 2.12.2 LVDS or eDP (optional)
- 5.14.1 Table 16: LVDS or eDP pins
- 5.15 2.12.3 HDMI-display
- 5.15.1 Table 17: HDMI pins
- 5.16 2.13 Camera
- 5.16.1 Table 17: Camera pins
- 5.17 2.14 Wireless
- 5.18 2.15 PCIe
- 5.18.1 Table 13: PCIe pins
- 6 3. Specifications
Generals
Description
The Wilk is powered by MediaTek Genio 700 or MediaTek Genio 510 Applications Processor. They are designed to meet the latest market requirements of connected streaming audio/video devices, scanning/imaging devices and various devices demanding high-performance and low-power.
The Genio 510 features advanced implementation of a dual ARM® Cortex®-A78 core, which operates at speeds of up to 2.0GHz and four ARM® Cortex®-A55 core, which operates at speeds of up to 2.0GHz
The Genio 700 features advanced implementation of a dual ARM® Cortex®-A78 core, which operates at speeds of up to 2.2GHz and six ARM® Cortex®-A55 core, which operates at speeds of up to 2.0GHz.
An Mali G57 MC3 GPU is also integrated as Cadence Tensilica VP6 with MediaTek APU3.0 for AI Acceleration.
A 64-bit LPDDR4 interface is used for memory. There are a number of other interfaces for connecting peripherals, such as displays, cameras, GPS and sensors, which are extended by components already available on the module:
eMMC (up to 64 GByte)
upto 2x 1Gbit Ethernet
TPM
1x USB 3.1 2x USB 2.0
MIPI/eDP, HDMI/DP
RTC
EEPROM
WLAN 802.11 a/b/g/n/ac and BT 5.3 Combo module (M.2 1216)
SMARC Standard
The SMARC (“Smart Mobility ARChitecture”) is a versatile small form factor computer Module definition targeting applications that require low power, low costs, and high performance. The Modules will typically use ARM SOCs similar or the same as those used in many familiar devices such as tablet computers and smart phones. Alternative low power SOCs and CPUs, such as tablet oriented x86 devices and other RISC CPUs may be used as well.
The Module power envelope is typically under 6W although designs up to about 15W are possible.
Block Diagram
Features and Interfaces
Features
Processor
MediaTek Genio 700 ARM® Octa-core CPU (Dual Cortex-A78 @ 2.2 GHz and Six Cortex-A55 @ 2.0 GHz)
MediaTek Genio 510 ARM® Six-core CPU (Dual Cortex-A78 @ 2.0 GHz and Four Cortex-A55 @ 2.0 GHz)
Mali G57 MC3 GPU
AI Accelerator: Cadence Tensilica VP6 with MediaTek APU3.0
System Companion Chip: MDSP RV55
DSP: Cadence Tensilica HiFi5
Memory
Up to 8GByte of 64-bit LPDDR4-4000
Storage
Up to 64 GByte eMMC
Wireless
WLAN 802.11 a/b/g/n/ac/ax
BT 5.3
MicroRF-antenna connector
Power
PMIC to generate all internal and external voltages from 3.3V up to 5V supply.
Dimensions
(Length x Width x Height): 82.0 x 50.0 x 5.4 mm
Interfaces / Signals accessible over connector
Power Supply through 5.0VDC +- 5%, +3.2V_RTC
LVDS Dual Channel or eDP (factory alternatives) up to 2560x1600p60
HDMI or DP (factory alternatives) up to 4K60
SD 4-bit interface (boot device)1
2x Gigabit Ethernet interfaces
1x USB 2.0 OTG port
up to 4x USB 2.0 using optional internal 2.0 Hub
1x I2S port
2x UART (4-wires)
2x UART (2-wires)
1x CAN interfaces (via SPI CAN Controller)
13x GPIOs
1 x MIPI_CSI0 2 Lanes Camera interface
1 x MIPI_CSI1 4 Lanes Camera Interface
1x General Purpose I2C Bus
2x PWM ports
TPM
Technical Documents
1. Pin description
The main connector of the WILK is the J2800 SMARC connector.
J500 may be used for debugging, programming and testing.
On the top side are UFL antenna connectors for the on-board WLAN + BT chip.
1.1 Pin description
The following signals are present at the SMARC connector.
Table 1: J2800: SMARC connector
Signal | Pin |
| Pin | Signal |
|---|---|---|---|---|
|
|
| S1 | I2C6_SCL |
SMB_ALERT# | P1 |
| S2 | I2C6_SDA |
GND | P2 |
| S3 | GND |
CSI1_CK_P | P3 |
| S4 | - |
CSI1_CLK_N | P4 |
| S5 | I2C5_SCL |
- | P5 |
| S6 | - |
- | P6 |
| S7 | I2C5_SDA |
CSI1_RX0_P | P7 |
| S8 | CSI0_CK_P |
CSI1_RX0_N | P8 |
| S9 | CSI0_CK_N |
GND | P9 |
| S10 | GND |
CSI1_RX1_P | P10 |
| S11 | CSI0_RX0_P |
CSI1_RX1_N | P11 |
| S12 | CSI0_RX0_N |
GND | P12 |
| S13 | GND |
CSI1_RX2_P | P13 |
| S14 | CSI0_RX1_P |
CSI1_RX2_N | P14 |
| S15 | CSI0_RX1_N |
GND | P15 |
| S16 | GND |
CSI1_RX3_P | P16 |
| S17 | GBE1_MDIO_P |
CSI1_RX3_N | P17 |
| S18 | GBE1_MDIO_N |
GND | P18 |
| S19 | GBE1_LINK100# |
GBEO_MDI3_N | P19 |
| S20 | GBE1_MDI1_P |
GBEO_MDI3_P | P20 |
| S21 | GBE1_MDI1_N |
GBEO_LINK100# | P21 |
| S22 | - |
GBEO_LINK1000# | P22 |
| S23 | - |
GBEO_MDI2_N | P23 |
| S24 | - |
GBEO_MDI2_P | P24 |
| S25 | GND |
GBEO_LINK_ACT# | P25 |
| S26 | - |
GBEO_MDI1_N | P26 |
| S27 | - |
GBEO_MDI1_P | P27 |
| S28 | USB_VDD33A |
- | P28 |
| S29 | - |
GBEO_MDI0_N | P29 |
| S30 | - |
GBEO_MDI0_P | P30 |
| S31 | GBE1_LINK_ACT# |
- | P31 |
| S32 | - |
GND | P32 |
| S33 | - |
- | P33 |
| S34 | GND |
SDIO_CMD | P34 |
| S35 | USB4_DP |
SDIO_CD# | P35 |
| S36 | USB4_DN |
SDIO_CK | P36 |
| S37 |
|
SDIO_PWR_EN_3V3 | P37 |
| S38 | I2SO_MCK |
GND | P38 |
| S39 | I2S0_LRCK |
SDIO_D0 | P39 |
| S40 | - |
SDIO_D1 | P40 |
| S41 | I2S0_SDIN |
SDIO_D2 | P41 |
| S42 | I2S0_CK |
SDIO_D3 | P42 |
| S43 | - |
SPIO_CS0# | P43 |
| S44 | - |
SPIO_CK | P44 |
| S45 | - |
SPIO_DIN | P45 |
| S46 | - |
SPIO_DO | P46 |
| S47 | GND |
GND | P47 |
| S48 | I2C_GP_CK |
- | P48 |
| S49 | I2C_GP_DAT |
- | P49 |
| S50 | I2S2_LRCK |
GND | P50 |
| S51 | I2S2_SDOUT |
- | P51 |
| S52 | - |
- | P52 |
| S53 | I2S2_CK |
GND | P53 |
| S54 | - |
ESPI_CS0# | P54 |
| S55 | USB5_EN_OC# |
- | P55 |
| S56 | ESPI_IO_2 |
ESPI_CK | P56 |
| S57 | ESPI_IO_3 |
ESPI_IO_1 | P57 |
| S58 | - |
ESPI_IO_0 | P58 |
| S59 | USB5_DP |
GND | P59 |
| S60 | USB5_DN |
USB0_DP | P60 |
| S61 | GND |
USB0_DN | P61 |
| S62 |
|
USB0_EN_OC# | P62 |
| S63 |
|
USB0_VBUS_DET | P63 |
| S64 | GND |
USB0_OTG_ID | P64 |
| S65 |
|
USB1_DP | P65 |
| S66 |
|
USB1_DN | P66 |
| S67 | GND |
USB1_EN_OC# | P67 |
| S68 | USB3_DP |
GND | P68 |
| S69 | USB3_DN |
USB2_DP | P69 |
| S70 | GND |
USB2_DN | P70 |
| S71 | USB2_SS_TXP |
USB2_EN_OC# | P71 |
| S72 | USB2_SS_TXN |
STM32_RST# | P72 |
| S73 | GND |
- | P73 |
| S74 | USB2_SS_RXP |
USB3_EN_OC# | P74 |
| S75 | USB2_SS_RXN |
|
|
|
|
|
EXT_PCIE_A_RST# | P75 |
| S76 | - |
USB4_EN_OC# | P76 |
| S77 | - |
PCIE_B_CKREQ# | P77 |
| S78 | - |
PCIE_A_CKREQ#_CON | P78 |
| S79 | - |
GND | P79 |
| S80 | GND |
- | P80 |
| S81 | - |
- | P81 |
| S82 | - |
GND | P82 |
| S83 | GND |
REF_CLKP_CARRIER | P83 |
| S84 | - |
REF_CLKN_CARRIER | P84 |
| S85 | - |
GND | P85 |
| S86 | GND |
PCIE_RXP_CARRIER | P86 |
| S87 | - |
PCIE_RXN_CARRIER | P87 |
| S88 | - |
GND | P88 |
| S89 | GND |
PCIE_TXP_CARRIER | P89 |
| S90 | - |
PCIE_TXN_CARRIER | P90 |
| S91 | - |
GND | P91 |
| S92 | GND |
HDMI_D2+ | P92 |
| S93 | DP0_LANE0+ |
HDMI_D2- | P93 |
| S94 | DP0_LANE0- |
GND | P94 |
| S95 | DP0_AUX_SEL |
HDMI_D1+ | P95 |
| S96 | DP0_LANE1+ |
HDMI_D1- | P96 |
| S97 | DP0_LANE1- |
GND | P97 |
| S98 | DP0_HPD_EXT |
HDMI_D0+ | P98 |
| S99 | DP0_LANE2+ |
HDMI_D0- | P99 |
| S100 | DP0_LANE2- |
GND | P100 |
| S101 | GND |
HDMI_CK+ | P101 |
| S102 | DP0_LANE3+ |
HDMI_CK- | P102 |
| S103 | DP0_LANE3- |
GND | P103 |
| S104 |
|
HDMI_HPD_EXT | P104 |
| S105 | DP0_AUX+ |
HDMI_CTRL_CK | P105 |
| S106 | DP0_AUX- |
HDMI_CTRL_DAT | P106 |
| S107 | LCD1_BKLT_EN |
DP1_AUX_SEL | P107 |
| S108 | LVDS1_EDP_CLK_P |
GPIO0/CAM0_PWR# | P108 |
| S109 | LVDS1_EDP_CLK_N |
GPIO1/CAM1_PWR# | P109 |
| S110 | GND |
GPIO2/CAM0_RST# | P110 |
| S111 | LVDS1_EDP_D0_P |
GPIO3/CAM1_RST# | P111 |
| S112 | LVDS1_EDP_D0_N |
GPIO4 | P112 |
| S113 | EDP1_HPD_EXT |
GPIO5 | P113 |
| S114 | LVDS1_EDP_D1_P |
GPIO6 | P114 |
| S115 | LVDS1_EDP_D1_N |
GPIO7 | P115 |
| S116 | LCD1_VDD_EN |
GPIO8 | P116 |
| S117 | LVDS1_TX2_P |
GPIO9 | P117 |
| S118 | LVDS1_TX2_N |
GPIO10 | P118 |
| S119 | GND |
GPIO11 | P119 |
| S120 | LVDS1_TX3_P |
GND | P120 |
| S121 | LVDS1_TX3_N |
I2C_PM_CK | P121 |
| S122 | LCD1_BKLT_PWM |
I2C_PM_DAT | P122 |
| S123 | GPIO13 |
BOOT_SEL0# | P123 |
| S124 | GND |
BOOT_SEL1# | P124 |
| S125 | LVDS0_TX0_P |
BOOT_SEL2# | P125 |
| S126 | LVDS0_TX0_N |
RESET_OUT# | P126 |
| S127 | LCD0_BKLT_EN |
RESET_IN# | P127 |
| S128 | LVDS0_TX1_P |
POWER_BTN# | P128 |
| S129 | LVDS0_TX1_N |
SER0_TX | P129 |
| S130 | GND |
SER0_RX | P130 |
| S131 | LVDS0_TX2_P |
SER0_RTS# | P131 |
| S132 | LVDS0_TX2_N |
SER0_CTS# | P132 |
| S133 | LCD0_VDD_EN |
GND | P133 |
| S134 | LVDS0_CK_P |
SER1_TX | P134 |
| S135 | LVDS0_CK_N |
SER1_RX | P135 |
| S136 | GND |
SER2_TX | P136 |
| S137 | LVDS0_TX3_P |
SER2_RX | P137 |
| S138 | LVDS0_TX3_N |
SER2_RTS# | P138 |
| S139 | I2C0_SCL |
SER2_CTS# | P139 |
| S140 | I2C0_SDA |
SER3_TX | P140 |
| S141 | LVDS0_BKLT_PWM |
SER3_RX | P141 |
| S142 | GPIO12 |
GND | P142 |
| S143 | GND |
CAN0_TX | P143 |
| S144 | EDP0_HPD |
CAN0_RX | P144 |
| S145 | WDT_TIME_OUT# |
| P145 |
| S146 | EXT_PCIE_WAKE# |
| P146 |
| S147 | VDD_RTC |
5V_SLEEP | P147 |
| S148 | LID# |
5V_SLEEP | P148 |
| S149 | SLEEP# |
5V_SLEEP | P149 |
| S150 | VIN_PWR_BAD# |
5V_SLEEP | P150 |
| S151 | CHARGING# |
5V_SLEEP | P151 |
| S152 | CHARGER_PRSNT# |
5V_SLEEP | P152 |
| S153 | CARRIER_STBY# |
5V_SLEEP | P153 |
| S154 | CARRIER_PWR_ON |
5V_SLEEP | P154 |
| S155 | FORCE_RECOV# |
5V_SLEEP | P155 |
| S156 | BATLOW# |
5V_SLEEP | P156 |
| S157 | TEST# |
|
|
| S158 | GND |
Table 2: J500: GENIO 700 JTAG connector:
This flex-cable connector uses the SMARC JTAG connector standard.
Pin | Signal |
|---|---|
1 | 1V8_RUN_PTC |
2 | JTAG_TRST# |
3 | JTAG_TMS |
4 | JTAG_TDO |
5 | JTAG_TDI |
6 | JTAG_TCK |
7 | - |
8 | 1V8_RUN_PTC (10K pullup) |
9 | (10K pulldown) |
10 | GND |
1.2 Electrical pin information
PI: | Power Input |
| DO: | Digital Output |
PO: | Power Output |
| DIO: | Digital Input/Output |
|
|
| DDI: | Differential Input |
AI: | Analog Input |
| DDO: | Differential Output |
AO: | Analog Output |
| DDIO: | Differential Input/Output |
|
|
|
|
|
DI: | Digital Input |
| OD | Open-Drain Output |
|
|
|
|
|
PD: | Pull-Down | (PDp: Pull-Down, Pull-behavior can be changed by software) |
|
|
PU: | Pull-Up | PUp: Pull-Up, Pull-behavior can be changed by software |
|
|
If two “types” are specified, the first value determines the type of primary function.
Table 3: SMARC pin information
Pin | Name | Type | Voltage | Connected to |
|---|---|---|---|---|
P1 | SMB_ALERT# | DI, PU(10K) | 1V8 | STM32, pin M2, port PA5 |
P2 | GND | Ground | ||
P3 | CSI1_CK_P | DDI | 1V2 | GENIO 700 |
P4 | CSI1_CLK_N | DDI | 1V2 | GENIO 700 |
P5 | - |
|
|
|
P6 | - |
|
|
|
P7 | CSI1_RX0_P | DDI | 1V2 | GENIO 700 |
P8 | CSI1_RX0_N | DDI | 1V2 | GENIO 700 |
P9 | GND | Ground | ||
P10 | CSI1_RX1_P | DDI | 1V2 | GENIO 700 |
P11 | CSI1_RX1_N | DDI | 1V2 | GENIO 700 |
P12 | GND | Ground | ||
P13 | CSI1_RX2_P | DDI | 1V2 | GENIO 700 |
P14 | CSI1_RX2_N | DDI | 1V2 | GENIO 700 |
P15 | GND | Ground | ||
P16 | CSI1_RX3_P | DDI | 1V2 | GENIO 700 |
P17 | CSI1_RX3_N | DDI | 1V2 | GENIO 700 |
P18 | GND | Ground | ||
P19 | GBEO_MDI3_N | DDIO | 3V3 | Gbit Ethernet-Phy |
P20 | GBEO_MDI3_P | DDIO | 3V3 | Gbit Ethernet-Phy |
P21 | GBEO_LINK100# | DO, PU(10K) | 3V3 | Gbit Ethernet-Phy |
P22 | GBEO_LINK1000# | DO, PU(4K7) | 3V3 | Gbit Ethernet-Phy |
P23 | GBEO_MDI2_N | DDIO | 3V3 | Gbit Ethernet-Phy |
P24 | GBEO_MDI2_P | DDIO | 3V3 | Gbit Ethernet-Phy |
P25 | GBEO_LINK_ACT# | DO, PU(10K) | 3V3 | Gbit Ethernet-Phy |
P26 | GBEO_MDI1_N | DDIO | 3V3 | Gbit Ethernet-Phy |
P27 | GBEO_MDI1_P | DDIO | 3V3 | Gbit Ethernet-Phy |
P28 | - |
|
|
|
P29 | GBEO_MDI0_N | DDIO | 3V3 | Gbit Ethernet-Phy |
P30 | GBEO_MDI0_P | DDIO | 3V3 | Gbit Ethernet-Phy |
P31 | - |
|
|
|
P32 | GND | Ground | ||
P33 | - |
|
|
|
P34 | SDIO_CMD | DO; PU(10K) | 1V8 or 3V3 | GENIO 700 |
P35 | SDIO_CD# | DI, PU(10K) | 1V8 or 3V3 | GENIO 700 |
P36 | SDIO_CK | DO | 1V8 or 3V3 | GENIO 700 |
P37 | SDIO_PWR_EN_3V3 | DO | 3V3 | GENIO 700 |
P38 | GND | Ground | ||
P39 | SDIO_D0 | DIO | 1V8 or 3V3 | GENIO 700 |
P40 | SDIO_D1 | DIO | 1V8 or 3V3 | GENIO 700 |
P41 | SDIO_D2 | DIO | 1V8 or 3V3 | GENIO 700 |
P42 | SDIO_D3 | DIO | 1V8 or 3V3 | GENIO 700 |
P43 | SPIO_CS0# | DO | 1V8 | GENIO 700 |
P44 | SPIO_CK | DO | 1V8 | GENIO 700 |
P45 | SPIO_DIN | DI | 1V8 | GENIO 700 |
P46 | SPIO_DO | DO | 1V8 | GENIO 700 |
P47 | GND | Ground | ||
P48 | - |
|
|
|
P49 | - |
|
|
|
P50 | GND | Ground | ||
P51 | - |
|
|
|
P52 | - |
|
|
|
P53 | GND | Ground | ||
P54 | ESPI_CS0# | DO | 1V8 | GENIO 700 |
P55 | - |
|
|
|
P56 | ESPI_CK | DO | 1V8 | GENIO 700 |
P57 | ESPI_IO_1 | DIO | 1V8 | GENIO 700 |
P58 | ESPI_IO_0 | DIO | 1V8 | GENIO 700 |
P59 | GND | Ground | ||
P60 | USB0_DP | DDIO | 3V3 | GENIO 700 |
P61 | USB0_DN | DDIO | 3V3 | GENIO 700 |
P62 | USB0_EN_OC# | DI,DO,PU(10K) | 3V3 | STM32, pin K1, port PC0 |
P63 | USB0_VBUS_DET | DI, PD(10K) | 3V3 | GENIO 700 |
P64 | USB0_OTG_ID | DI | 3V3 | GENIO 700 |
P65 | USB1_DP | DDIO | 3V3 | USB Hub or |
P66 | USB1_DN | DDIO | 3V3 | USB Hub or |
P67 | USB1_EN_OC# | DI,DO,PU(10K) | 3V3 | STM32, pin K2, port PC2 |
P68 | GND | Ground | ||
P69 | USB2_DP | DDIO | 3V3 | USB Hub (optional) |
P70 | USB2_DN | DDIO | 3V3 | USB Hub (optional) |
P71 | USB2_EN_OC# | DI,DO,PU | 3V3 | USB Hub (optional) |
P72 | STM32_RST# | DI, PU(10K) | 1V8 | STM32, pin G2 |
P73 | - |
|
|
|
P74 | USB3_EN_OC# | DI,DO,PU(10K) | 3V3 | STM32, pin M1, port PA2 |
P75 | EXT_PCIE_A_RST# | D0 | 1V8 | GENIO 700 |
P76 | USB4_EN_OC# | DI,DO,PU | 3V3 | USB Hub (optional) |
P77 | PCIE_B_CKREQ# | DI, DO | 1V8 | STM32, pin C11, port PA13 |
P78 | PCIE_A_CKREQ# | DI | 1V8 | STM32, pin B12 |
P79 | GND | Ground | ||
P80 | - |
|
|
|
P81 | - |
|
|
|
P82 | GND | Ground | ||
P83 | REF_CLKP_CARRIER | DD0 | 1V8 | GENIO 700 |
P84 | REF_CLKN_CARRIER | DD0 | 1V8 | GENIO 700 |
P85 | GND | Ground | ||
P86 | PCIE_RXP_CARRIER | DDI | 1V8 | GENIO 700 |
P87 | PCIE_RXN_CARRIER | DDI | 1V8 | GENIO 700 |
P88 | GND | Ground | ||
P89 | PCIE_TXP_CARRIER | DDO | 1V8 | GENIO 700 |
P90 | PCIE_TXN_CARRIER | DDO | 1V8 | GENIO 700 |
P91 | GND | Ground | ||
P92 | HDMI_D2+ | DDO | 1V8 | GENIO 700 |
P93 | HDMI_D2- | DDO | 1V8 | GENIO 700 |
P94 | GND | Ground | ||
P95 | HDMI_D1+ | DDO | 1V8 | GENIO 700 |
P96 | HDMI_D1- | DDO | 1V8 | GENIO 700 |
P97 | GND | Ground | ||
P98 | HDMI_D0+ | DDO | 1V8 | GENIO 700 |
P99 | HDMI_D0- | DDO | 1V8 | GENIO 700 |
P100 | GND | Ground | ||
P101 | HDMI_CK+ | DDO | 1V8 | GENIO 700 |
P102 | HDMI_CK- | DDO | 1V8 | GENIO 700 |
P103 | GND | Ground | ||
P104 | HDMI_HPD | PD (1M) | 1V8 | GENIO 700 |
P105 | HDMI_CTRL_CK | PD (100K) | 1V8 | GENIO 700 |
P106 | HDMI_CTRL_DAT | PD (100K) | 1V8 | GENIO 700 |
P107 | DP1_AUX_SEL | PD (1M) |
| not connected |
P108 | GPIO0/CAM0_PWR# | DIO | 1V8 | GENIO 700 |
P109 | GPIO1/CAM1_PWR# | DIO | 1V8 | GENIO 700 |
P110 | GPIO2/CAM0_RST# | DIO | 1V8 | GENIO 700 |
P111 | GPIO3/CAM1_RST# | DIO | 1V8 | GENIO 700 |
P112 | GPIO4 | DIO | 1V8 | STM32, Pin M8, Port PE8 |
P113 | GPIO5 | DIO | 1V8 | STM32, Pin K8, Port PE9 |
P114 | GPIO6 | DIO | 1V8 | STM32, Pin L8, Port PE10 |
P115 | GPIO7 | DIO | 1V8 | STM32, Pin M9, Port PE11 |
P116 | GPIO8 | DIO | 1V8 | STM32, Pin L9, Port PE12 |
P117 | GPIO9 | DIO | 1V8 | STM32, Pin M10, Port PE13 |
P118 | GPIO10 | DIO | 1V8 | STM32, Pin K9, Port PE14 |
P119 | GPIO11 | DIO | 1V8 | STM32, Pin L10, Port PE15 |
P120 | GND | Ground | ||
P121 | I2C_PM_CK | DO, PU(4K7) | 1V8 | STM32, Pin C4, Port PB6 |
P122 | I2C_PM_DAT | DIO, PU(4K7) | 1V8 | STM32, Pin B3 Port PB7 |
P123 | BOOT_SEL0# | DI, PU(10K) | 1V8 | STM32, Pin L11, Port PB11 |
P124 | BOOT_SEL1# | DI, PU(10K) | 1V8 | STM32, Pin M12, Port PB13 |
P125 | BOOT_SEL2# | DI, PU(10K) | 1V8 | STM32, Pin L12, Port PA8 |
P126 | RESET_OUT# | DO | 1V8 | STM32, Pin K12, Port PC7 |
P127 | RESET_IN# | DI, PU(10K) | 1V8 | STM32, Pin G11, Port PD11 |
P128 | POWER_BTN# | DI, PU(10K) | 1V8 | STM32, Pin E10, Port PA10 |
P129 | SER0_TX | DO | 1V8 | GENIO 700 |
P130 | SER0_RX | DI, PU(100K) | 1V8 | GENIO 700 |
P131 | SER0_RTS# | DO | 1V8 | GENIO 700 |
P132 | SER0_CTS# | DI, PU(100K) | 1V8 | GENIO 700 |
P133 | GND | Ground | ||
P134 | SER1_TX | DO | 1V8 | GENIO 700 |
P135 | SER1_RX | DI, PU(100K) | 1V8 | GENIO 700 |
P136 | SER2_TX | DO | 1V8 | GENIO 700 (optional) |
P137 | SER2_RX | DI, PU(100K) | 1V8 | GENIO 700 (optional) |
P138 | SER2_RTS# | DO | 1V8 | GENIO 700 (optional) |
P139 | SER2_CTS# | DI, PU(100K) | 1V8 | GENIO 700 (optional) |
P140 | SER3_TX | DO | 1V8 | GENIO 700 |
P141 | SER3_RX | DI, PU(100K) | 1V8 | GENIO 700 |
P142 | GND | Ground | ||
P143 | CAN0_TX | DO | 1V8 | CAN controller |
P144 | CAN0_RX | DI | 1V8 | CAN controller |
P145 |
|
|
|
|
P146 |
|
|
|
|
P147 | 5V_SLEEP | PI | 5V0 |
|
P148 | 5V_SLEEP | PI | 5V0 |
|
P149 | 5V_SLEEP | PI | 5V0 |
|
P150 | 5V_SLEEP | PI | 5V0 |
|
P151 | 5V_SLEEP | PI | 5V0 |
|
P152 | 5V_SLEEP | PI | 5V0 |
|
P153 | 5V_SLEEP | PI | 5V0 |
|
P154 | 5V_SLEEP | PI | 5V0 |
|
P155 | 5V_SLEEP | PI | 5V0 |
|
P156 | 5V_SLEEP | PI | 5V0 |
|
S1 | I2C6_SCL | DO, PU(4K7) | 1V8 | GENIO 700 |
S2 | I2C6_SDA | DIO, PU(4K7) | 1V8 | GENIO 700 |
S3 | GND | Ground | ||
S4 | - |
|
|
|
S5 | I2C5_SCL | DO, PU(4K7) | 1V8 | GENIO 700 |
S6 | - |
|
|
|
S7 | I2C5_SDA | DIO, PU(4K7) | 1V8 | GENIO 700 |
S8 | CSI0_CK_P | DDI | 1V2 | GENIO 700 |
S9 | CSI0_CK_N | DDI | 1V2 | GENIO 700 |
S10 | GND | Ground | ||
S11 | CSI0_RX0_P | DDI | 1V2 | GENIO 700 |
S12 | CSI0_RX0_N | DDI | 1V2 | GENIO 700 |
S13 | GND | Ground | ||
S14 | CSI0_RX1_P | DDI | 1V2 | GENIO 700 |
S15 | CSI0_RX1_N | DDI | 1V2 | GENIO 700 |
S16 | GND | Ground | ||
S17 | GBE1_MDIO_P | DDIO, PU(49R9) | USB_VDD33A | LAN9514 |
S18 | GBE1_MDIO_N | DDIO, PU(49R9) | USB_VDD33A | LAN9514 |
S19 | GBE1_LINK100# | DO | USB_VDD33A | LAN9514 |
S20 | GBE1_MDI1_P | DDIO, PU(49R9) | USB_VDD33A | LAN9514 |
S21 | GBE1_MDI1_N | DDIO, PU(49R9) | USB_VDD33A | LAN9514 |
S22 | - |
|
|
|
S23 | - |
|
|
|
S24 | - |
|
|
|
S25 | GND | Ground | ||
S26 | - |
|
|
|
S27 | - |
|
|
|
S28 | USB_VDD33A |
|
|
|
S29 | - |
|
|
|
S30 | - |
|
|
|
S31 | GBE1_LINK_ACT# | DO | USB_VDD33A | LAN9514 |
S32 | - |
|
|
|
S33 | - |
|
|
|
S34 | GND | Ground | ||
S35 | USB4_DP | DDIO | 3V3 | USB Hub (optional) |
S36 | USB4_DN | DDIO | 3V3 | USB Hub (optional) |
S37 |
|
|
|
|
S38 | I2SO2_MCK | DO | 1V8 | GENIO 700 |
S39 | I2S0_LRCK | DIO | 1V8 | GENIO 700 |
S40 | - |
|
|
|
S41 | I2S0_SDIN | DI | 1V8 | GENIO 700 |
S42 | I2S0_CK | DO | 1V8 | GENIO 700 |
S43 | - |
|
|
|
S44 | - |
|
|
|
S45 | - |
|
|
|
S46 | - |
|
|
|
S47 | GND | Ground | ||
S48 | I2C_GP_CK | DO, PU(4K7) | 1V8 | GENIO 700 |
S49 | I2C_GP_DAT | DIO, PU(4K7) | 1V8 | GENIO 700 |
S50 | I2S2_LRCK | DIO | 1V8 | GENIO 700 |
S51 | I2S2_SDOUT | DO | 1V8 | GENIO 700 |
S52 | - |
|
|
|
S53 | I2S2_CK | DO | 1V8 | GENIO 700 |
S54 | - |
|
|
|
S55 | USB5_EN_OC# | DI,DO,PU | 3V3 | USB Hub (optional) |
S56 | ESPI_IO_2 | DIO | 1V8 | GENIO 700 |
S57 | ESPI_IO_3 | DIO | 1V8 | GENIO 700 |
S58 | - |
|
|
|
S59 | USB5_DP | DDIO | 3V3 | USB Hub (optional) |
S60 | USB5_DN | DDIO | 3V3 | USB Hub (optional) |
S61 | GND | Ground | ||
S62 |
|
|
|
|
S63 |
|
|
|
|
S64 | GND | Ground | ||
S65 |
|
|
|
|
S66 |
|
|
|
|
S67 | GND | Ground | ||
S68 | USB3_DP | DDIO | 3V3 | GENIO 700 |
S69 | USB3_DN | DDIO | 3V3 | GENIO 700 |
S70 | GND | Ground | ||
S71 | USB2_SS_TXP | DDO |
| GENIO 700 |
S72 | USB2_SS_TXN | DDO |
| GENIO 700 |
S73 | GND | Ground | ||
S74 | USB2_SS_RXP | DDI |
| GENIO 700 |
S75 | USB2_SS_RXN | DDI |
| GENIO 700 |
S76 | - |
|
|
|
S77 | - |
|
|
|
S78 | - |
|
|
|
S79 | - |
|
|
|
S80 | GND | Ground | ||
S81 | - |
|
|
|
S82 | - |
|
|
|
S83 | GND | Ground | ||
S84 | - |
|
|
|
S85 | - |
|
|
|
S86 | GND | Ground | ||
S87 | - |
|
|
|
S88 | - |
|
|
|
S89 | GND | Ground | ||
S90 | - |
|
|
|
S91 | - |
|
|
|
S92 | GND | Ground | ||
S93 | DP0_LANE0+ | DDO | 1V8 | GENIO 700 |
S94 | DP0_LANE0- | DDO | 1V8 | GENIO 700 |
S95 | DP0_AUX_SEL | PD(1M) |
| not connected |
S96 | DP0_LANE1+ | DDO | 1V8 | GENIO 700 |
S97 | DP0_LANE1- | DDO | 1V8 | GENIO 700 |
S98 | DP0_HPD_EXT | DI | 1V8 | GENIO 700 |
S99 | DP0_LANE2+ | DDO | 1V8 | GENIO 700 |
S100 | DP0_LANE2- | DDO | 1V8 | GENIO 700 |
S101 | GND | Ground | ||
S102 | DP0_LANE3+ | DDO | 1V8 | GENIO 700 |
S103 | DP0_LANE3- | DDO | 1V8 | GENIO 700 |
S104 |
|
|
|
|
S105 | DP0_AUX+ | DDO, PD(100K) | 3V3 | GENIO 700 |
S106 | DP0_AUX- | DDO, PU(100K) | 3V3 | GENIO 700 |
S107 | LCD1_BKLT_EN | DO | 1V8 | GENIO 700 |
S108 | LVDS1_EDP_CLK_P | DDO | 1V8 | MIPI to LVDS bridge |
S109 | LVDS1_EDP_CLK_N | DDO | 1V8 | MIPI to LVDS bridge |
S110 | GND | Ground | ||
S111 | LVDS1_EDP_D0_P | DDO | 1V8 | MIPI to LVDS bridge |
S112 | LVDS1_EDP_D0_N | DDO | 1V8 | MIPI to LVDS bridge |
S113 | EDP1_HPD_EXT | DI, PD(1M) | 1V8 | GENIO 700 |
S114 | LVDS1_EDP_D1_P | DDO | 1V8 | MIPI to LVDS bridge |
S115 | LVDS1_EDP_D1_N | DDO | 1V8 | MIPI to LVDS bridge |
S116 | LCD1_VDD_EN | DO | 1V8 | GENIO 700 |
S117 | LVDS1_TX2_P | DDO | 1V8 | MIPI to LVDS bridge |
S118 | LVDS1_TX2_N | DDO | 1V8 | MIPI to LVDS bridge |
S119 | GND | Ground | ||
S120 | LVDS1_TX3_P | DDO | 1V8 | MIPI to LVDS bridge |
S121 | LVDS1_TX3_N | DDO | 1V8 | MIPI to LVDS bridge |
S122 | LCD1_BKLT_PWM | DO | 1V8 | GENIO 700 |
S123 | GPIO13 | DIO | 1V8 | STM32, Pin E11, Port PD14 |
S124 | GND | Ground | ||
S125 | LVDS0_TX0_P | DDIO | 1V8 | MIPI to LVDS bridge |
S126 | LVDS0_TX0_N | DDIO | 1V8 | MIPI to LVDS bridge |
S127 | LVDS0_BKLT_EN | DO | 1V8 | GENIO 700 |
S128 | LVDS0_TX1_P | DDIO | 1V8 | MIPI to LVDS bridge |
S129 | LVDS0_TX1_N | DDIO | 1V8 | MIPI to LVDS bridge |
S130 | GND | Ground | ||
S131 | LVDS0_TX2_P | DDIO | 1V8 | MIPI to LVDS bridge |
S132 | LVDS0_TX2_N | DDIO | 1V8 | MIPI to LVDS bridge |
S133 | LVDS0_VDD_EN | DO | 1V8 | GENIO 700 |
S134 | LVDS0_CK_P | DDIO | 1V8 | MIPI to LVDS bridge |
S135 | LVDS0_CK_N | DDIO | 1V8 | MIPI to LVDS bridge |
S136 | GND | Ground | ||
S137 | LVDS0_TX3_P | DDIO | 1V8 | MIPI to LVDS bridge |
S138 | LVDS0_TX3_N | DDIO | 1V8 | MIPI to LVDS bridge |
S139 | I2C0_SCL | DO, PU(4K7) | 1V8 | GENIO 700 |
S140 | I2C0_SDA | DIO, PU(4K7) | 1V8 | GENIO 700 |
S141 | LVDS0_BKLT_PWM | DO | 1V8 | GENIO 700 |
S142 | GPIO12 | DIO | 1V8 | STM32, Pin E12, Port PD13 |
S143 | GND | Ground | ||
S144 | EDP0_HPD | PD(1M) |
| not connected |
S145 | WDT_TIME_OUT# | DO | 1V8 | STM32, Pin J11, Port PC6 |
S146 | EXT_PCIE_WAKE# | DI | 1V8 | GENIO 700 |
S147 | VDD_RTC | PI | 3V0 | |
S148 | LID# | DI, PU(10K) | 1V8 | STM32, Pin D12, PA11 |
S149 | SLEEP# | DI, PU(10K) | 1V8 | STM32, Pin C12, PA12 |
S150 | VIN_PWR_BAD# | DI |
| Power management |
S151 | CHARGING# | DI, PU(10K) | 1V8 | STM32, Pin D10, Port PF8 |
S152 | CHARGER_PRSNT# | DI, PU(10K) | 1V8 | STM32, Pin H11, Port PD9 |
S153 | CARRIER_STBY# | DO | 1V8 | STM32, Pin M4, Port PC5 |
S154 | CARRIER_PWR_ON | DO | 1V8 | STM32, Pin L3, Port PA4 |
S155 | FORCE_RECOV# | DI, PU(10K) | 1V8 | STM32, Pin H12, Port PD10 |
S156 | BATLOW# | DI, PU(10K) | 1V8 | STM32, Pin B11, Port PA15 |
S157 | TEST# | DI, PU(10K) | 1V8 | STM32, Pin L2, Port PA1 |
S158 | GND | Ground | ||
2. Interfaces
This chapter includes a short description of all interfaces of the WILK. Please consult the processor datasheet for detailed information.
2.1 Power Supply
The WILK can be supplied by a single +5.0V power supply.
Table 4: Power Supply pins
Name | Description |
|---|---|
5V_SLEEP | 5V power input. This supply controls the STM32. STM32 MCU controls reset and power to the GENIO 700 processor. |
GND | Ground input |
VDD_RTC | 3V power supply to supply the RTC on the WILK |
2.2 Control signals
Table 5: Control Signal pins
Name | Description |
|---|---|
RESET_IN# | Negated reset input. 0: reset device, 1: normal operation |
RESET_OUT# | Negated reset output. 0: device in reset, 1: normal operation (active low) |
BOOT_SEL[2…0] | tell the module what physical device to do a BCT boot from, not used! The boot device selection for the WILK is done via assembly options. A distinction is only made between booting from SPI NOR flash or eMMC (standard). |
STM32_RST# | Negated reset input for STM32. 0: reset STM32, 1: normal operation (active low) |
POWER_BTN# | Carrier based power button (active low) |
WDT_TIME_OUT# | Watchdog output (active low) |
LID# | Lid open/close indication input (active low) |
SLEEP# | Sleep indicator input (active low) |
VIN_PWR_BAD# | Power status input. 0: Carrierrboard power is not ready to support WILK |
CHARGING# | Input, held low by carrier during battery scharging, float when charging is complete (active low) |
CHARGER_PRSNT# | Input, held low by Carrier if DC input for battery charger is present (active low) |
CARRIER_STBY# | Power status output. If the power save state standby |
CARRIER_PWR_ON | Power status output. It is a signal to Carrier that the |
FORCE_RECOV# | Primary boot media can be re-initialized (active low) |
BATLOW# | Input, battery low indication to Module. Carrier to float the line in inactive state (active low) |
TEST# | Negated test input of STM32. 0: device in programming mode, 1: normal operation (active low) |
2.3 UART
The GENIO 700 provides 4 Universal Asynchronous Receiver/Transmitter. With a transceiver these signals can be converted to RS232, RS485 or IrDA.
Following UART ports are accessible through the SMARC connector:
Table 7: UART pins
Name | Description |
|---|---|
SER0_TX | Serial 0 transmit output |
SER0_RX | Serial 0 receive input |
SER0_RTS# | Serial 0 request to send output (active low) |
SER0_CTS# | Serial 0 clear to send input (active low) |
SER1_TX | Serial 1 transmit output |
SER1_RX | Serial 1 receive input |
SER2_TX | Serial 2 transmit output |
SER2_RX | Serial 2 receive input |
SER2_RTS# | Serial 2 request to send output (active low) |
SER2_CTS# | Serial 2 clear to send input (active low) |
SER3_TX | Serial 3 transmit output |
SER3_RX | Serial 3 receive input |
Baudrate: High-speed TIA/EIA-232-F compatible, up to 1Mbit/s, IrDA-compatible, up to 115.2 Kbit/s
Data-Bits: 7 or 8 bits (RS232) or 9 bit (RS485)
Stop Bits: 1, 2
Parity: None, Even, Odd
Features: Hardware flow control (RTS, CTS)
2.4 SPI
The Serial Peripheral Interface is a programmable synchronous serial port, which may be used to connect to a multiple of different peripherals.
Table 8: SPI pins
Name | Description |
|---|---|
SPIO_CS0# | SPI 0 slave select |
SPI0_CK | SPI 0 clock |
SPI0_DIN | SPI 0 data in |
SPI0_DO | SPI 0 data out |
Speed: up to xxx MHz
2.5 eSPI
The enhanced Serial Peripheral Interface is a programmable synchronous serial port, which may be used to connect to a multiple of different peripherals.
Table 8: SPI pins
Name | Description |
|---|---|
ESPI_CS0# | eSPI slave select |
ESPI_CK | eSPI clock |
ESPI_IO_0 | eSPI data 0 in/out |
ESPI_IO_1 | eSPI data 1 in/out |
ESPI_IO_2 | eSPI data 2 in/out |
ESPI_IO_3 | eSPI data 3 in/out |
2.6 I2C
The Inter-Integrated Circuit (I2C ) provides functionality of a standard I2C master and slave.
Table 9: I2C pins
Name | Description |
|---|---|
I2C0_SCL | I2C0 clock |
I2C0_SDA | I2C0 data |
I2C3_SCL | I2C3 clock |
I2C3_SDA | I2C3 data |
I2C_GP_CK | I2C GP clock |
I2C_GP_DAT | I2C GP data |
I2C5_SCL | I2C5 clock |
I2C5_SDA | I2C5 data |
I2C_PM_CK | I2C PM clock |
I2C_PM_DAT | I2C PM data |
Speed: Standard mode, up to 100kbit/s
Fast mode, up to 400 kbit/s
Features: Multimaster operation.
I2C Bus specification version 2.1
2.7 I2S
The Inter-IC sound interface provides a synchronous audio interface (SAI) and is used to connect to audio codecs.
Table 10: I2S pins
Name | Description |
|---|---|
I2S0_LRCK | I2S0 Left & Right Synchronisation Clock |
I2S0_SDIN | I2S0 Digital Audio Input |
I2S0_CK | I2S0 Digital Audio Clock |
I2S2_LRCK | I2S2 Left & Right Synchronisation Clock |
I2S2_SDOUT | I2S2 Digital Audio Output |
I2S2_CK | I2S2 Digital Audio Clock |
2.8 SDIO
The SDIO interface may be used to connect a SD-Card, eMMC or SDIO hardware.
Table 11: SDIO pins
Name | Description |
|---|---|
SDIO_CMD | SDIO command output |
SDIO_CD# | SDIO card detect input (active low) |
SDIO_CK | SDIO clk output |
SDIO_PWR_EN_3V3 | SDIO Power enable signal |
SDIO_D0 | SDIO data bit 0 |
SDIO_D1 | SDIO data bit 1 |
SDIO_D2 | SDIO data bit 2 |
SDIO_D3 | SDIO data bit 3 |
Speed: Card bus clock frequency up to 208 MHz
Features: Conforms to the SD Host Controller Standard Specification version 3.0.
Compatible with the MMC System Specification version 4.2/4.3/4.4/4.41/5.0.
Compatible with the SD Memory Card Specification version 3.0 and supports the Extended Capacity SD Memory Card
Compatible with the SDIO Card Specification version 3.0
2.9 USB
In the standard configuration, the WILK offers one USB 3.1 port and two USB 2.0 ports, which are routed to the SMARC connector. As an assembly option, a quad USB hub is possible, so that up to five USB ports are possible on the SMARC connector.
Table 12: USB pins
Name | Description |
|---|---|
USB0_DP | USB Port 0 data (positive), USB2.0 |
USB0_DN | USB Port 0 data (negative), USB2.0 |
USB0_EN_OC# | USB Port 0 power enable output and overcurrent input (active low) |
USB0_VBUS_DET | USB Port 0 VBUS detection |
USB0_OTG_ID | USB Port 0 ID detect |
USB1_DP | USB Port 1 data (positive), USB2.0 |
USB1_DN | USB Port 1 data (negative), USB2.0 |
USB1_EN_OC# | USB Port 1 power enable output and overcurrent input (active low) |
USB2_DP | USB Port 2 data (positive) (optional) |
USB2_DN | USB Port 2 data (negative) (optional) |
USB2_EN_OC# | USB Port 2 power enable output and overcurrent input (active low) (optional) |
USB2_SS_TXP | USB Port 2 super speed transmit (positive), USB3.1 |
USB2_SS_TXN | USB Port 2 super speed transmit (negative), USB3.1 |
USB2_SS_RXP | USB Port 2 super speed receive (positive), USB3.1 |
USB2_SS_RXN | USB Port 2 super speed receive (negative), USB3.1 |
USB3_DP | USB Port 3 data (positive) (optional), USB2.0 |
USB3_DN | USB Port 3 data (negative) (optional), USB2.0 |
USB3_EN_OC# | USB Port 3 power enable output and overcurrent input (active low) |
USB4_DP | USB Port 4 data (positive) (optional), USB2.0 |
USB4_DN | USB Port 4 data (negative) (optional), USB2.0 |
USB4_EN_OC# | USB Port 4 power enable output and overcurrent input (active low) (optional) |
USB5_DP | USB Port 5 data (positive) (optional), USB2.0 |
USB5_DN | USB Port 5 data (negative) (optional), USB2.0 |
USB5_EN_OC# | USB Port 5 power enable output and overcurrent input (active low) (optional) |
Speed: High-speed 480Mbit/s
Full-speed 12Mbit/s
Low-speed 1.5Mbit/s
Features: Complies with USB specification rev. 2.0
2.10 Ethernet
The WILK uses a Realtek RTL8211 integrated 10/100/1000 Mbps Ethernet Transceiver to interface with the GENIO 700 RGMII and a LAN9514 for 10/100 Mbit Ethernet communication.
Table 13: Ethernet pins
Name | Description |
|---|---|
GBE0_MDI0_P | ETH port 0 differential pair 0 positive signal |
GBE0_MDI0_N | ETH port 0 differential pair 0 negative signal |
GBE0_MDI1_P | ETH port 0 differential pair 1 positive signal |
GBE0_MDI1_N | ETH port 0 differential pair 1 negative signal |
GBE0_MDI2_P | ETH port 0 differential pair 2 positive signal |
GBE0_MDI2_N | ETH port 0 differential pair 2 negative signal |
GBE0_MDI3_P | ETH port 0 differential pair 3 positive signal |
GBE0_MDI3_N | ETH port 0 differential pair 3 negative signal |
GBE0_LINK100# | ETH port 0 Link Speed indication LED for GBE0 100Mbps (active low) |
GBE0_LINK1000# | ETH port 0 Link Speed indication LED for GBE0 1000Mbps (active low) |
GBE0_LINK_ACT# | ETH port 0 Link / Activity Indication LED driven Low on Link (10, 100 or 1000Mbps) Blinks on Activity (active low) |
GBE1_MDI0_P | ETH port 1 differential pair 0 positive signal |
GBE1_MDI0_N | ETH port 1 differential pair 0 negative signal |
GBE1_MDI1_P | ETH port 1 differential pair 1 positive signal |
GBE1_MDI1_N | ETH port 1 differential pair 1 negative signal |
GBE1_LINK100# | ETH port 1 Link Speed indication LED for GBE0 100Mbps (active low) |
GBE1_LINK_ACT# | ETH port 1 Link / Activity Indication LED driven Low on Link (10, 100 or 1000Mbps) Blinks on Activity (active low) |
2.11 CAN
The WILK uses an MCP2518 SPI to CAN converter.
Table 14: CAN pins
Name | Description |
|---|---|
CAN0_TX | CAN 0 transmit data |
CAN0_RX | CAN 0 receive data |
2.12 Display
2.12.1 LVDS-display
Table 15: LVDS pins
Name | Description |
|---|---|
LVDS0_TX0_P | LVDS port 0 differential pair 0 positive signal |
LVDS0_TX0_N | LVDS port 0 differential pair 0 negative signal |
LVDS0_TX1_P | LVDS port 0 differential pair 1 positive signal |
LVDS0_TX1_N | LVDS port 0 differential pair 1 negative signal |
LVDS0_TX2_P | LVDS port 0 differential pair 2 positive signal |
LVDS0_TX2_N | LVDS port 0 differential pair 2 negative signal |
LVDS0_TX3_P | LVDS port 0 differential pair 3 positive signal |
LVDS0_TX3_N | LVDS port 0 differential pair 3 negative signal |
LVDS0_CK_P | LVDS port 0 differential clock pair positive signal |
LVDS0_CK_N | LVDS port 0 differential clock pair negative signal |
LCD0_BKLT_EN | Backlight enable signal port 0 |
LCD0_BKLT_PWM | Backlight PWM signal port 0 |
LCD0_VDD_EN | Power control signal port 0 |
2.12.2 LVDS or eDP (optional)
Table 16: LVDS or eDP pins
Name | Description |
|---|---|
LVDS1_EDP_D0_P | LVDS port 1 differential pair 0 positive signal |
LVDS1_EDP_D0_N | LVDS port 1 differential pair 0 negative signal |
LVDS1_EDP_D1_P | LVDS port 1 differential pair 1 positive signal |
LVDS1_EDP_D1_N | LVDS port 1 differential pair 1 negative signal |
LVDS1_EDP_D2_P | LVDS port 1 differential pair 2 positive signal |
LVDS1_EDP_D2_N | LVDS port 1 differential pair 2 negative signal |
LVDS1_EDP_D3_P | LVDS port 1 differential pair 3 positive signal |
LVDS1_EDP_D3_N | LVDS port 1 differential pair 3 negative signal |
LVDS1_EDP_CLK_P | LVDS port 1 differential clock pair positive signal |
LVDS1_EDP_CLK_N | LVDS port 1 differential clock pair negative signal |
LCD1_BKLT_EN | Backlight enable signal |
LCD1_BKLT_PWM | Backlight PWM signal |
LCD1_VDD_EN | Power control signal |
2.12.3 HDMI-display
Table 17: HDMI pins
Name | Description |
|---|---|
HDMI_D0+ | HDMI port differential pair 0 positive signal |
HDMI_D0- | HDMI port differential pair 0 negative signal |
HDMI_D1+ | HDMI port differential pair 0 positive signal |
HDMI_D1- | HDMI port differential pair 0 negative signal |
HDMI_D2+ | HDMI port differential pair 0 positive signal |
HDMI_D2- | HDMI port differential pair 0 negative signal |
HDMI_CK+ | HDMI port differential clock positive signal |
HDMI_CK- | HDMI port differential clock negative signal |
HDMI_HPD | HDMI Hot Plug Active High Detection Signal |
HDMI_CTRL_CK | I2C clock line dedicated to HDMI |
HDMI_CTRL_DAT | I2C data line dedicated to HDMI |
2.13 Camera
The GENIO 700 processor got two MIPI CSI camera interfaces. They are connected to the SMARC connector.
Table 17: Camera pins
Name | Description |
|---|---|
CSIO_CK_P | CSI port 0 differential clock pair positive signal |
CSIO_CK_N | CSI port 0 differential clock pair negative signal |
CSIO_RX0_P | CSI port 0 differential pair 0 positive signal |
CSIO_RX0_N | CSI port 0 differential pair 0 negative signal |
CSIO_RX1_P | CSI port 0 differential pair 1 positive signal |
CSIO_RX1_N | CSI port 0 differential pair 1 negative signal |
GPIO0/CAM0_PWR# | Camera 0 power enable signal (active low) |
GPIO2/CAM0_RST# | Camera 0 reset signal (active low) |
CSI1_CK_P | CSI port 1 differential clock pair positive signal |
CSI1_CK_N | CSI port 1 differential clock pair negative signal |
CSI1_RX0_P | CSI port 1 differential pair 0 positive signal |
CSI1_RX0_N | CSI port 1 differential pair 0 negative signal |
CSI1_RX1_P | CSI port 1 differential pair 1 positive signal |
CSI1_RX1_N | CSI port 1 differential pair 1 negative signal |
CSI1_RX2_P | CSI port 1 differential pair 2 positive signal |
CSI1_RX2_N | CSI port 1 differential pair 2 negative signal |
CSI1_RX3_P | CSI port 1 differential pair 3 positive signal |
CSI1_RX3_N | CSI port 1 differential pair 3 negative signal |
GPIO1/CAM1_PWR# | Camera 1 power enable signal (active low) |
GPIO3/CAM1_RST# | Camera 1 reset signal (active low) |
Speed:
Features
2.14 Wireless
The WILK may be equipped with a AzureWave CM276NF WiFi and BT module. The antennas are connected directly to the module.
2.15 PCIe
The PCIe bus can be used to connect various components.
Table 13: PCIe pins
Name | Description |
|---|---|
REF_CLKP_CARRIER | PCIE differential clock pair positive signal |
REF_CLKN_CARRIER | PCIE differential clock pair negative signal |
PCIE_RXP_CARRIER | PCIE differential receive positive signal |
PCIE_RXN_CARRIER | PCIE differential receive negative signal |
PCIE_TXP_CARRIER | PCIE differential transmit positive signal |
PCIE_TXN_CARRIER | PCIE differential transmit negative signal |
PCIE_A_RST# | PCIE reset signal output |
PCIE_A_CLKREQ#_CON | PCIE A clock request signal input |
PCIE_B_CLKREQ# | PCIE B clock request signal |
3. Specifications
3.1 Absolute Maximum Ratings
Absolute maximum ratings reflect conditions that the module may be exposed outside of the operating limits, without experiencing immediate functional failure. Functional operation is only expected during the conditions indicated under “Recommended Operating Conditions”. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the module. Exposure to absolute -maximum rated conditions for extended periods may affect device reliability.
| Pin | Min | Max | Unit |
|---|---|---|---|---|
Supply Voltage | 5V_SLEEP | -0.3 | 5.5 | V |
| VDD_RTC | -0.3 | 3.5 | V |
Storage Temperature | TStorage | -40 | +85 | °C |
3.2 Recommended Operating Conditions
| Pin | Min | Typ | Max | Unit |
|---|---|---|---|---|---|
Supply Voltage | 5V_SLEEP | 4.75 | 5.0 | 5.25 | V |
| VDD_RTC | 2.0 | 3.0 | 3.25 | V |
Supply current (typ.) | @ 5V_SLEEP Idle Using/Running Typ. Peak currents when running |
|
tbd tbd tbd |
|
mA mA A |
Operating temperature | TConsumer TExtended TIndustrial | 0 -25 -40 | +25 +25 +25 | +85 +85 +85 | °C °C °C |
3.3 ESD Ratings (tbd)
|
| Max | Unit |
|---|---|---|---|
V(ESD) | Human body model (HBM) Charged-device model (CDM) | +/-1000 +/-250 | V V |
3.4 Electrical characteristics
3.4.1 GENIO 700 GPIO DC parameters. Please view GENIO 700 datasheet for details:
| Parameter | Min | Max | Unit |
|---|---|---|---|---|
VIL_1V8 | Low-level input voltage | -0.3 | 0.35 x VDDIO | V |
VIH_1V8 | High-level input voltage | 0.65 x VDDIO | VDDIO + 0.3 | V |
VOL_1V8 | High-level output voltage |
| 0.25 x VDDIO | V |
VOH_1V8 | Low-level output voltage | 0.75 x VDDIO |
| V |
RP_up | Pull-Up Resistance |
|
| kOhm |
RP_down | Pull-Down Resistance |
|
| kOhm |
3.4.2 STM32 Cortex M0 GPIO DC parameters. Please view STM32 datasheet for details:
| Parameter | Min | Max | Unit |
|---|---|---|---|---|
VIL_1V8 | Low-level input voltage | - | 0.3 x VDDIO | V |
VIH_1V8 | High-level input voltage | 0.7 x x VDDIO | - | V |
VOL_1V8 | High-level output voltage | - | 0.4 | V |
VOH_1V8 | Low-level output voltage | VDDIO - 0.45 | - | V |
RP_up | Pull-Up Resistance | 25 (typ 40) | 55 | kOhm |
RP_down | Pull-Down Resistance | 25 (typ 40) | 55 | kOhm |
3.5 Mechanical Specification
Dimensions (mm) of the WILK module (top view)
ToDo: an updated image needs to be inserted