SBC-pITX-EHL (D63)
- Matteo Giustini
- Mattia Aisa
- Lorenzo Pagliai
Depending on the configuration and following revisions, the features of the board are subject to change. For detailed information on hardware specifications, please visit www.seco.com
SBC-pITX-EHL is a PicoITX compliant module with the Intel® Atom® x6000E Series and Intel® Pentium® and Celeron® N and J Series processors. Designed and optimized for Functional Safety (FuSa) applications, this module offers flexibility, reliability, and safety for a wide range of applications across multiple industries.
For ordering purposes, the SBC-pITX-EHL is referred to by its base code, “D63”.
INDEX
How can I use GPIO/I2C/SPI peripherals?
Please refer to the following instructions to prevent damage!
D63 has 2 connectors to use GPIOs and other peripherals like I2C, SPI, PWM and QEP. Here you can find the schematic:
To make those functionalities available on all boards, and for more flexibility, they are not multiplexed by HW, but is all managed in the BIOS setup. Here you can find a table on where functionalities are available:
Legend: SOC → Chipset peripheral
EC → Embedded controller peripheral
| Windows (RH Proxy) | Linux (Native driver) | EAPI |
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SOC SPI1 |
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SOC SPI3 |
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EC SPI |
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QEP0 |
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QEP1 |
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PWM1 (SOC PWM06) |
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PWM2 (SOC PWM02) |
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SOC I2C0 |
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EC I2C0 |
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SOC I2C1 |
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EC I2C1 |
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GPIO 0-7 (EC) |
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GPIO 0-7 (SOC) |
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By default, all pins are set as Input Hi-Z. So, if you want to use another funtionality, you need to enable it on setup. Here are 2 tables on how to enable peripherals and what you can use simultaneously:
| SOC SPI1 | SOC SPI3 | EC SPI | QEP0 | QEP1 | PWM1 (SOC PWM06) | PWM2 (SOC PWM02) | SOC I2C0 | EC I2C0 | SOC I2C1 | EC I2C1 | GPIO 0-7 (EC) | GPIO 0-7 (SOC) |
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SOC SPI1 |
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| 0-4 | 0-4 |
SOC SPI3 |
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EC SPI |
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QEP0 |
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| 0, 2-3 | 0, 2-3 |
QEP1 |
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| 5-7 | 5-7 |
PWM1 (SOC PWM06) |
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| 1 | 1 |
PWM2 (SOC PWM02) |
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| 4 | 4 |
SOC I2C0 |
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EC I2C0 |
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SOC I2C1 |
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EC I2C1 |
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GPIO 0-7 (EC) |
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GPIO 0-7 (SOC) |
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Peripheral | BIOS setup option to enable peripheral |
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Chipset SPI1 | Chipset → PCH-IO Configuration → PSE Configuration → SPI1 → Host owned with pin muxed |
Chipset SPI3 | Chipset → PCH-IO Configuration → PSE Configuration → SPI3 → Host owned with pin muxed |
MEC SPI | It is enabled automatically when first transmission request is done. Disable Chipset SPI3 before use it! |
QEP0 | Chipset → PCH-IO Configuration → PSE Configuration → QEP0 → Host owned with pin muxed |
QEP1 | Chipset → PCH-IO Configuration → PSE Configuration → QEP1 → Host owned with pin muxed |
PWM1 (Chipset PWM06) | Chipset → PCH-IO Configuration → PSE Configuration → PWM Pin Mux Selection → PWM6 → Enabled |
PWM2 (Chipset PWM02) | Chipset → PCH-IO Configuration → PSE Configuration → PWM Pin Mux Selection → PWM2 → Enabled |
Chipset I2C0 | Chipset → PCH-IO Configuration → SerialIo Configuration → I2C3 Controller → Enabled |
MEC I2C0 | It is enabled automatically when first transmission request is done. Disable Chipset I2C0 before use it! |
Chipset I2C1 | Chipset → PCH-IO Configuration → SerialIo Configuration → I2C1 Controller → Enabled |
MEC I2C1 | It is enabled automatically when first transmission request is done. Disable Chipset I2C1 before use it! |
GPIO 0-7 (MEC) | Advanced → Embedded Controller → GPIO Configurations → Configuration → <Select desired default> |
GPIO 0-7 (Chipset) | Disable conflicting functions if you want to use the pin as GPIO. GPIO pins can’t be used both from MEC and Chipset. MEC GPIO Pins has to be set as Input if you want to use Chipset GPIO pins |
What is loaded in a standard module?
Off-the-shelf products are shipped with a standard in-house-developed software.
The definition of standard, in this case, is “the environment which SECO adopts for validation”.
Anyway, custom in-house-developed software with different defaults can be built in accordance with customers' requirements submitting a new ticket.
The BIOS version updated in your module is shown in Aptio Setup Utility menu under:
Main page
Advanced > SMBIOS Information page
Other available BIOS versions:
Updating the BIOS
How can I update BIOS through AFU utility? - SECO Technical Resources - Confluence
Further Reading
Visit our Blog to find some tips!
Blog Posts
-
Using AMISCE to Update BIOS Settings
created by
06. Oct 2022
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How can I change BIOS logo?
created by
25. May 2021
-
How can I modify SMBIOS information?
created by
24. May 2021
-
How can I define a boot sequence in UEFI mode and perform pre-boot operations?
created by
17. May 2021
-
What is SecureBoot and how can I enable it?
created by
14. May 2021
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How can I boot from LAN?
created by
14. May 2021
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How can I create a bootable EFI USB device?
created by
14. May 2021
Downloads
Here you can find the latest version available:
BIOS | |
BIOS Tools | |
Driver WIN10 LTSC | seco_elkhartlake_driver_windows10-2021-ltsc_mr5-rs5-1.00.00.7z |
6.x.x Linux Kernel | |
EAPI |
Clea OS
This board is fully supported by Clea OS, the operating system for the All-In-One IIot CLEA platform developed by SECO and based on Yocto. Clea OS is intended to provide the highest standards in terms of security and stability through features such as OTA (Over the Air) updates, dual partitions and fallback procedures. Clea OS integrates a Device Manager to communicate with the Cloud and allows a family of products to be managed as a fleet.
Source code
The source code for Clea OS can be found at the following Gitlab organization. To build a complete Yocto image from source, you can follow the readme of the repo manifest.
Binaries
The Yocto image binaries associated with the various Clea OS releases can be found at the following Release page.