STM32 MCU - MAURY - REVB0

Owned by Lukas Rosky
Last updated: 23. Jul 2024
3 min read

Customers may request access to the source-code of the firmware to modify it for their needs.

Commands & Registers (I2C)

I2C-Address: 0x40 (7-bit)

Register

Name

Access

Description

Default Value

0x01

REG_ID

read

ID-Register

0xA5

0x02

REG_CONTROL

write

Restart and boot with BOOT_MODE=
0x00 - Internal Fuses
0x01 - Serial Download
0x02 - uSDHC1 8-bit eMMC 5.1
0x03 - uSDHC2 4-bit SD 3.0

0x04 - Power Off
0x05 - Reboot from BOOT_SEL pins

-

0x03

REG_CONFIG

-

-

-

0x04

REG_PIN_CONFIG

write

<Pin> <Parameter>
Parameter for GPIO:

0x01: Input, NoPull
0x10: Input, PullDown
0x11: Input, PullUp

0x20: Output PushPull, init low level
0x21: Output PushPull, init high level
0x40: Output, OpenDrain, init low level
0x41: Output, OpenDrain, init high level

0x80: IRQ Rising Edge
0x81: IRQ Falling Edge
0x82: IRQ Any Edge

-

0x05

REG_PIN_SET

write

<Pin> <Level>

-

0x06

REG_PIN_GET

write
read

<Pin>
Level of pin.

-

0x07

REG_PWM_CONFIG

write

<Pin> <Duty Cycle [%]>

-

0x08

REG_ALTERNATE_FUNCTION

write

Set Pin to specific alternate function.
For available alternate functions for pins refer to the list of configurable GPIO pins below.

<Pin> <Alternate Function>

Alternate Functions:
0x00: GPIO (Default: Input, NoPull)
0x01: PWM (Default: disabled)

 

0x09

REG_ADC_READ

-

-

-

0x0A

REG_INT_STATUS0

read

Read INT_STATUS1 register, clear it and reset EC_IRQ#_OD to “1” if all interrupts are read.

0x01: GPIO0/CAM0_PWR#
0x02: GPIO1/CAM1_PWR#
0x04: GPIO2/CAM0_RST#
0x08: GPIO3/CAM1_RST#
0x10: GPIO4
0x20: GPIO5
0x40: GPIO6
0x80: GPIO7

0x00

0x0B

REG_INT_ENABLE0

r/w

Read or update IRQ Enable Register.

Same signals as in REG_INT_STATUS0.

0x00

0x0C

REG_INT_STATUS1

read

Read INT_STATUS2 register, clear it and reset EC_IRQ#_OD to “1” if all interrupts are read.

0x01: GPIO8
0x02: GPIO9
0x04: GPIO_10
0x08: GPIO_11
0x10: GPIO12
0x20: GPIO13
0x40: RTC_INT#
0x80: SMB_ALERT#

0x00

0x0D

REG_INT_ENABLE1

r/w

Read or update IRQ Enable Register.

Same signals as in REG_INT_STATUS1.

0x00

0x0E

REG_INT_STATUS2

read

Read INT_STATUS3 register, clear it and reset EC_IRQ#_OD to “1” if all interrupts are read.

0x01: USB0_EN_OC#
0x02: USB1_EN_OC#
0x04: USB2_EN_OC#
0x08: USB3_EN_OC#
0x10: USB4_EN_OC#
0x20: CPU_IRQ#

0x00

0x0F

REG_INT_ENABLE2

r/w

Read or update IRQ Enable Register.

Same signals as in REG_INT_STATUS2.

 

0x10

REG_SHUTDOWN_DELAY

r/w

Read/write delay in 10ms steps before powering off during soft shutdown/restart.

(0x01 = 10ms, 0xFF = 2550 ms)

0x0A

0x80

REG_SECO_CODE

read

Read SECO_CODE

RE39-1FH2-1431-E2: 0x48

-

0x90

REG_RAM_CODE

-

-

-

0xF0

REG_VERSION

read

Read firmware version

0x01

 

Configurable GPIO Pins (I2C)

The following Pins are configurable via I2C:

Pin#

Name

Default Configuration

IRQ

Alternate Function

Pin#

Name

Default Configuration

IRQ

Alternate Function

0

GPIO0/CAM0_PWR#

Input, NoPull

 

1

GPIO1/CAM1_PWR#

Input, NoPull

 

2

GPIO2/CAM0_RST#

Input, NoPull

 

3

GPIO3/CAM1_RST#

Input, NoPull

 

4

GPIO4

Input, NoPull

 

5

GPIO5

Input, NoPull

*

PWM

6

GPIO6

Input, NoPull

 

7

GPIO7

Input, NoPull

 

8

GPIO8

Input, NoPull

 

9

GPIO9

Input, NoPull

 

10

GPIO_10

Input, NoPull

 

11

GPIO_11

Input, NoPull

 

12

GPIO12

Input, NoPull

*

 

13

GPIO13

Input, NoPull

*

 

14

RTC_INT#

(IRQ only)

 

15

SMB_ALERT#

(IRQ only)

*

 

16

USB0_EN_OC#

Output, OpenDrain, init low level

 

17

USB1_EN_OC#

Output, OpenDrain, init low level

 

18

USB2_EN_OC#

Output, OpenDrain, init low level

*

 

19

USB3_EN_OC#

Output, OpenDrain, init low level

*

 

20

USB4_EN_OC#

Output, OpenDrain, init low level

*

 

21

CPU_IRQ#

(IRQ only)

*

 

22

USB_HUB_PEN

Output, PushPull, init low level

 

 

23

USB_HUB_RST#_1V8

Output, PushPull, init low level

 

 

24

ENET0_RST#_1V8

Output, PushPull, init low level

 

 

25

ENET1_RST#_1V8

Output, PushPull, init low level

 

 

26

EDP_BRG_EN

Output, PushPull, init low level

 

 

27

LCD0_VDD_EN

Output, PushPull, init low level

 

 

28

LCD0_BKLT_EN

Output, PushPull, init low level

 

 

29

LCD0_BKLT_PWM

PWM, disabled

 

GPIO

30

LCD1_VDD_EN

Output, PushPull, init low level

 

 

31

LCD1_BKLT_EN

Output, PushPull, init low level

 

 

32

LCD1_BKLT_PWM

PWM, disabled

 

GPIO

33

WIFI_DISABLE

Output, PushPull, init high level

 

 

34

WIFI_CLK_EN

Output, PushPull, init low level

 

 

35

WIFI_PWRDWN#

Output, PushPull, init low level

 

 

36

RESET_OUT#

Output, PushPull, init low level, set high ~100ms after startup (-> SMARC Spec.)

 

 

37

I2S0_MCK

PWM, disabled

 

 

*: Polled IRQ

Carrier board BOOT_SEL configuration

The BOOT_SEL[2:0] Configuration on the carrier board is used to determine the boot device by setting the BOOT_MODE[3:0] pins:

BOOT_SEL[2:0]#

BOOT_MODE[3:0]

Boot Device

BOOT_SEL[2:0]#

BOOT_MODE[3:0]

Boot Device

0 0 1

0 0 1 1

Carrier SD Card

1 0 0

0 0 0 0

Boot from Fuse (default)

1 0 1

0 0 0 1

Serial Download Mode

1 1 0

0 0 1 0

Module eMMC

Any other BOOT_SEL configuration will be treated like the default option.

Connecting FORCE_RECOV# to GND will cause the STM32 to always set the BOOT_MODE to Serial Download Mode.

Other Functions

  • Holding the RESET button for >= 10 seconds will cause the system to reboot into serial download mode rather than rebooting into the mode selected by the BOOT_SEL configuration of the carrier board.