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  • Trizeps VIII Mini (SOM-Trizeps-VIII-MX8M-Mini)

     

    Description

    The Trizeps VIII Mini is powered by NXP i.MX 8M Mini processor, which is designed to meet the latest market requirements of connected streaming audio/video devices, scanning/imaging devices and various devices demanding high-performance and low-power.

    The i.MX 8M Mini family of processors features advanced implementation of a quad ARM® Cortex®-A53 core, which operates at speeds of up to 1.8GHz (consumer version) and 1.5GHz (industrial version). A general purpose Cortex®-M4 core processor is for low-power processing. A 32-bit LPDDR4 is used for memory. There are a number of other i.MX 8M Mini interfaces for connecting peripherals, such as displays, cameras, GPS and sensors, which are extended by components already available on the module:

    • a stereo, hi-fi quality audio-codec.

    • a FPGA with up to 4300 LUT to convert parallel display/camera/data-streams to/from MIPI and for user defined programmable logic.

    • a programmable Cortex-M0 Kinetis MCU for realtime processing, capable of reading multiple 16bit analog inputs, usable as resistive touch-controller and for CAN communication.

    • WLAN 802.11 a/b/g/n/ac and BT 4.2 / 5 module

    The Trizeps VIII Mini module got a SODIMM200 card edge connector and a 60pin FX11 high-speed board connector. The pinning of both connectors is to a large extent compatible to previous Trizeps modules. The main difference is the GBit Ethernet feature, which use the pins of the now missing parallel address-/databus.

    Difference to Trizeps VIII

    The i.MX8M Mini processor of Trizeps VIII Mini benefits from advanced 14nm LPC FinFET Technology, which allows for lesser power-consumption and higher operating frequencies than the i.MX8 used on Trizeps VIII.

    The Trizeps VIII offers more interfaces:

    • HDMI

    • support of 4K displays

    • two USB3.0 instead of USB2.0 ports.

    • additional 4ch MIPI CSI port.

    • larger L2 cache.

    The GPIO pinning between both modules is kept the same for maximum compatibility.

    Difference to Trizeps VIII Nano

    The i.MX 8M Nano processor of Trizeps VIII Nano is similiar to the i.MX 8M Mini processor used on Trizeps VIII Mini, but has less features.

    The Trizeps VIII Nano lacks some interfaces:

    • VPU

    • PCIe

    • only one USB2.0 port.

    • 16bit instead of 32bit LPDDR4.

    The GPIO pinning between both modules is kept the same for maximum compatibility. 10 GPIO SODIMM-pins ( 110,112,114,-,130) are not connected on Trizeps VIII Nano.

    Block Diagram

    Technical Documents

    Datasheet / Datenblatt: TrizepsVIII-Mini_Datasheet_V3.1

    Changes of key components over the revisions

     

    Ethernet PHY

    LVDS transceiver

    Audio Codec

     

    Ethernet PHY

    LVDS transceiver

    Audio Codec

    V1R1

    Qualcomm AR8031

    TI SN65DSI8x

    Cirrus WM8983

    V1R2

    Qualcomm AR8031

    TI SN65DSI8x

    Cirrus WM8983

    V1R3

    Qualcomm AR8031

    TI SN65DSI8x

    Cirrus WM8983

    V2R1

    REALTEK RTL8211

    QuickLogic ArcticLink-III-BX6

    Cirrus WM8983

    V2R2

    REALTEK RTL8211

    QuickLogic ArcticLink-III-BX6

    Cirrus WM8983

    V3R1

    REALTEK RTL8211

    QuickLogic ArcticLink-III-BX6

    Cirrus WM8962

    Features and Interfaces

    Features

    Processor:

    NXP i.MX 8M Mini ARM® Quad Cortex-A53 at up to 1.8GHz (consumer), 1.6GHz (industrial)
    NXP i.MX 8M Mini ARM® Cortex-M4
    NXP Kinetis V ARM® Cortex-M0+ at up to 75MHz

    Memory:

    1 or 2 GByte of 32-bit LPDDR4-3200
    Higher densities are available on request.

    Storage:

    Micro-SD socket or
    4 or 8 GByte eMMC
    Higher densities are available on request.

    Wireless:

    WLAN 802.11 a/b/g/n/ac
    BT 4.2 and BT 5.0 ready
    Micro RF-antenna connector

    Power:

    PMIC to generate all internal and external voltages from 3.3V supply.

    Dimensions:

    (Length x Width x Height):      67.6 x 36.7 x 6.4 mm

    Interfaces / Signals accessible over connectors

    • Power Supply through +3.3V.

    • 2x USB2.0 OTG port (USB Host or Slave).

    • PCIe

    • SD/SDIO Card Interface

    • 4x UART

    • SPI and Quad-SPI

    • 2x I2C

    • Mipi Display (4ch) or Single/Dual LVDS or parallel RGB Display.

    • 1x Mipi Camera (4ch).

    • 1Gbit,100/10Mbit Ethernet

    • 1x CAN

    • 2x 4ch 16bit ADC

    • Stereo Headphone

    • Stereo Line-In

    • Microphone input

    • 1W Speaker output

    • SPDIF In and Out

    • Multi-Channel Serial-Audio-Interface

    • GPIO, PWM

     

    1 Pin-description

    The main connector of the Trizeps VIII Mini is the SODIMM200 connector.
    To operate, only +3V3 and GND pins need to be connected. Leave unused pins unconnected.
    The U14 Board2Board connector can be omitted if the signals are not needed.
    J1 and J2 may be used for debugging, programming and testing.
    On the bottom side are UFL antenna connectors for the on-board WLAN + BT chip.

     

    J2: FPGA and MCU JTAG               
                  J1: i.MX 8M Mini JTAG                                                                             

    U14: Board2Board Connector

    Figure 1-1: Connectors

    1.1      Pin-Description (Primary Function)

    The i.MX8M Mini processor, the Cortex M0+ MCU and the FPGA are highly configurable devices, where each pin may have multiple different functions.
    The pin-names are derived from previous Trizeps-versions and their primary or most interesting function.
    Please view chapter “1.2 Pin-Mux Information” for details on how these pins may be configured by software.

    Notes:

    *1) In the table below, some of the old Trizeps pin-names are placed in brackets [ ] for reference.

    *2) FPGA_CIF_D[9..0]  / SAIx_RXD[7..0], FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are routed to the FPGA and the i.MX 8M. In the following documentation they are either named FPGA_CIF_Dx or SAIx_RXDy, depending if the FPGA or i.MX 8M function is described.

    *3) FPGA_CIF_VSYNC, FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are connected to i.MX 8M pins, if the FPGA is not mounted (RA3).

    *4) BT_PCM_IN, BT_PCM_OUT, BT_PCM_SYNC and BT_PCM_CLK are connected to the on-board BT-module if it is mounted!

    *5) PCIE_CLKREQ may not be usable when Wifi module is mounted.

     J500: SODIMM Connector

    Signal

    Pin

     

    Pin

    Signal

    AUDIO_MIC_OUT

    1

     

    2

    VIN_AD3 (MCU)

    AUDIO_MIC_GND

    3

     

    4

    VIN_AD2 (MCU)

    AUDIO_LINEIN_L

    5

     

    6

    VIN_AD1 (MCU)

    AUDIO_LINEIN_R

    7

     

    8

    VIN_AD0 (MCU)

    AUDIO_AGND

    9

     

    10

    AUDIO_VDDA

    AUDIO_AGND

    11

     

    12

    AUDIO_VDD_SPEAKER

    AUDIO_HEADPHONE_GND

    13

     

    14

    TSPX (MCU)

    AUDIO_HEADPHONE_L

    15

     

    16

    TSMX (MCU)

    AUDIO_HEADPHONE_R

    17

     

    18

    TSPY (MCU)

    UART3_RXD

    19

     

    20

    TSMY (MCU)

    UART3_TXD

    21

     

    22

    SPIN22_RTS3

    UART1_DTR

    23

     

    24

    SPIN24_CTS3

    UART1_CTS

    25

     

    26

    RESET_IN

    UART1_RTS

    27

     

    28

    SPEAKER_R

    UART1_DSR

    29

     

    30

    SPEAKER_L

    UART1_DCD

    31

     

    32

    UART2_CTS

    UART1_RXD

    33

     

    34

    UART2_RTS

    UART1_TXD

    35

     

    36

    UART2_RXD

    UART1_RI

    37

     

    38

    UART2_TXD

    GND

    39

     

    40

    VCC (+3V3)

    GND

    41

     

    42

    VCC (+3V3)

    SPIN43

    43

     

    44

    FPGA_LCD_DE

    SPIN45

    45

     

    46

    FPGA_LCD_D07

    SD2_CLK

    47

     

    48

    FPGA_LCD_D09

    SAI1_RXD0

    49

     

    50

    FPGA_LCD_D11

    SD2_DATA3

    51

     

    52

    FPGA_LCD_D12

    SAI1_RXD1

    53

     

    54

    FPGA_LCD_D13

    SPIN55

    55

     

    56

    FPGA_LCD_PCLK

    SAI1_RXD2

    57

     

    58

    FPGA_LCD_D03

    SD2_DETECT

    59

     

    60

    FPGA_LCD_D02

    SAI1_RXD3

    61

     

    62

    FPGA_LCD_D08

    SAI1_RXD4

    63

     

    64

    FPGA_LCD_D15

    SAI1_RXD5

    65

     

    66

    FPGA_LCD_D14

    SAI1_RXD6

    67

     

    68

    FPGA_LCD_HSYNC

    LED_GPIO

    69

     

    70

    FPGA_LCD_D01

    SAI1_RXD7

    71

     

    72

    FPGA_LCD_D05

    SAI5_RXD1

    73

     

    74

    FPGA_LCD_D10

    SAI5_RXD2

    75

     

    76

    FPGA_LCD_D00

    BACKLIGHT_PWM

    77

     

    78

    FPGA_LCD_D04

    POWERFAIL

    79

     

    80

    FPGA_LCD_D06

    SD2_DATA1

    81

     

    82

    FPGA_LCD_VSYNC

    GND

    83

     

    84

    VCC (+3V3)

    SD2_DATA2

    85

     

    86

    FPGA_CIF_VSYNC (*3)

    RESET_OUT

    87

     

    88

    SAI1_MCLK (*3)

    +3V3_AUX

    89

     

    90

    SAI1_RXC (*3)

    +3V3_AUX

    91

     

    92

    SAI1_RXFS (*3)

    SPIN93 [RD/WR]

    93

     

    94

    I2C1_SCL

    SPIN95 [RDY]

    95

     

    96

    I2C1_SDA

    CAN1_RX (MCU)

    97

     

    98

    GPIO_AUX

    CAN1_TX (MCU)

    99

     

    100

    DISPLAY_ENABLE

    SPIN101

    101

     

    102

    AUDIO_ENABLE

    SPIN103

    103

     

    104

    SPIN104

    QSPI_SCLK [CS1]

    105

     

    106

    SAI5_MCLK

    QSPI_SS0 [CS3]

    107

     

    108

    VCC (+3V3)

    GND

    109

     

    110

    SAI1_TXD0 [A08]

    QSPI_DATA0 [A00]

    111

     

    112

    SAI1_TXD1 [A09]

    QSPI_DATA1 [A01]

    113

     

    114

    SAI1_TXD2 [A10]

    PCIE_CLKREQ (*5)

    115

     

    116

    SAI1_TXD3 [A11]

    QSPI_DATA2 [A03]

    117

     

    118

    SAI1_TXD4 [A12]

    QSPI_DATA3 [A04]

    119

     

    120

    SAI1_TXD5 [A13]

    SPIN121 [A05]

    121

     

    122

    SAI1_TXD6 [A14]

    CSI1_PWDN [A06]

    123

     

    124

    SAI1_TXD7 [A15]

    CSI1_RESET [A07]

    125

     

    126

    SAI1_TXFS [DQM0]

    USB1_PEN

    127

     

    128

    SAI1_TXC [DQM1]

    USB2_PEN

    129

     

    130

    -

    USB2_OC

    131

     

    132

    SPIN132

    USB1_OC

    133

     

    134

    SPIN134

    USB1_VBUS

    135

     

    136

    SPIN136

    USB1_ID

    137

     

    138

    -

    USB1_DP

    139

     

    140

    -

    USB1_DN

    141

     

    142

    -

    USB2_DP

    143

     

    144

    -

    USB2_DN

    145

     

    146

    BT_PCM_IN [A19] (*4)

    GND

    147

     

    148

    VCC (+3V3)

    -

    149

     

    150

    FPGA_LCD_D16

    -

    151

     

    152

    FPGA_LCD_D17

    -

    153

     

    154

    PCIE_WAKE

    -

    155

     

    156

    VDD_FPGA_MIPI

    -

    157

     

    158

    PCIE_REFCLK_N

    SPDIF_IN [D05]

    159

     

    160

    PCIE_REFCLK_P

    SPDIF_OUT [D06]

    161

     

    162

    PCIE_TXN_P

    SPDIF_EXT_CLK [D07]

    163

     

    164

    PCIE_TXN_N

    -

    165

     

    166

    PCIE_RXN_P

    -

    167

     

    168

    PCIE_RXN_N

    VDD_ENET_IO [D10]

    169

     

    170

    FPGA_LCD_D21

    ETH_LED_SPEED1000 [D11]

    171

     

    172

    FPGA_LCD_D20

    ETH_TRX2_N [D12]

    173

     

    174

    FPGA_LCD_D19

    ETH_TRX2_P [D13]

    175

     

    176

    FPGA_LCD_D18

    ETH_TRX3_N [D14]

    177

     

    178

    FPGA_LCD_D23

    ETH_TRX3_P [D15]

    179

     

    180

    FPGA_LCD_D22

    GND

    181

     

    182

    VCC (+3V3)

    ETH_LED_LINK_AKT

    183

     

    184

    BT_PCM_OUT (*4)

    ETH_LED_SPEED

    185

     

    186

    BT_PCM_CLK (*4)

    ETH_TRX0_N

    187

     

    188

    BT_PCM_SYNC (*4)

    ETH_TRX0_P

    189

     

    190

    SD2_CMD

    ETH_GND

    191

     

    192

    SD2_DATA0

    ETH_TRX1_N

    193

     

    194

    I2C2_SDA

    ETH_TRX1_P

    195

     

    196

    I2C2_SCL

    GND

    197

     

    198

    VCC (+3V3)

    GND

    199

     

    200

    VCC_SNVS (+3V3)

     

    J400: Board2Board Connector

    Signal

    Pin

     

    Pin

    Signal

    MIPI_CSI1_D2_P

    1

     

    2

    MIPI_DSI_D3_P

    MIPI_CSI1_D2_N

    3

     

    4

    MIPI_DSI_D3_N

    MIPI_CSI1_D3_P

    5

     

    6

    MIPI_DSI_D2_P

    MIPI_CSI1_D3_N

    7

     

    8

    MIPI_DSI_D2_N

    -

    9

     

    10

    LVDS1_TX2_P

    GND

    11

     

    12

    GND

    -

    13

     

    14

    LVDS1_TX2_N

    -

    15

     

    16

    LVDS1_TX3_N

    -

    17

     

    18

    LVDS1_TX3_P

    -

    19

     

    20

    LVDS1_CLK_P

    -

    21

     

    22

    LVDS1_CLK_N

    -

    23

     

    24

    LVDS1_TX0_P

    -

    25

     

    26

    LVDS1_TX0_N

    -

    27

     

    28

    LVDS1_TX1_P

    -

    29

     

    30

    LVDS1_TX1_N

    MIPI_DSI_D1_P

    31

     

    32

    MIPI_DSI_D1_N

    GND

    33

     

    34

    GND

    LVDS0_TX1_N

    35

     

    36

    MIPI_DSI_CLK_N

    LVDS0_TX1_P

    37

     

    38

    MIPI_DSI_CLK_P

    LVDS0_TX0_P

    39

     

    40

    -

    LVDS0_TX0_N

    41

     

    42

    -

    LVDS0_CLK_N

    43

     

    44

    -

    LVDS0_CLK_P

    45

     

    46

    -

    LVDS0_TX2_P

    47

     

    48

    -

    LVDS0_TX2_N

    49

     

    50

    -

    LVDS0_TX3_P

    51

     

    52

    -

    LVDS0_TX3_N

    53

     

    54

    -

    GND

    55

     

    56

    GND

    MIPI_DSI_D0_N

    57

     

    58

    -

    MIPI_DSI_D0_P

    59

     

    60

    -

    MIPI_CSI1_D0_N

    61

     

    62

    MIPI_CSI1_CLK_N

    MIPI_CSI1_D0_P

    63

     

    64

    MIPI_CSI1_CLK_P

    MIPI_CSI1_D1_P

    65

     

    66

    MIPI_CSI1_D1_N

    GND

    67

     

    68

    GND

     

     J1: i.MX8M JTAG Connector

    This flex-cable-connector uses the SECO JTAG connector standard. An Adapter to Multi-ICE pin-header is available.

    Pin

    Signal

    1

    +3V3_AUX

    2

    GND

    3

    JTAG_TMS

    4

    JTAG_TRST_N

    5

    JTAG_TCK

    6

    JTAG_TDO

    7

    JTAG_TDI

    8

    JTAG_RESET_N

     

    J2: FPGA & MCU JTAG Connector

    This flex-cable-connector uses the SECO JTAG connector standard. An adapter to Multi-ICE pin-header is available.

    Pin

    Signal

    1

    VDD_FPGA_MIPI

    2

    GND

    3

    FPGA_JTAG_TMS

    4

    SWD_CLK

    5

    FPGA_JTAG_TCK

    6

    FPGA_JTAG_TDO

    7

    FPGA_JTAG_TDI

    8

    SWD_DIO

     

    1.2      Pin-Mux Information

    Several pins are GPIOs which may be configured for different functions by software.
    Please check with the processor datasheet for additional pin-mux information.
    An Excel-Sheet with pin-information is available at: https://documentation.seco.com/service/doku.php/service/hardware/module/sodimm200

    Notes:

    *2) FPGA_CIF_D[9..0]  / SAIx_RXD[7..0], FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are routed to the FPGA and the i.MX 8M Mini. In the following documentation they are either named FPGA_CIF_Dx or SAIx_RXDy, depending if the FPGA or i.MX 8M Mini function is described.

    *3) FPGA_CIF_VSYNC, FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are connected to i.MX 8M Mini pins, if the FPGA is not mounted (RA3).

    *4) BT_PCM_IN, BT_PCM_OUT, BT_PCM_SYNC and BT_PCM_CLK are connected to the on-board BT-module if it is mounted!

    *5) PCIE_CLKREQ may not be usable when Wifi module is mounted.

     1.2.1 i.MX 8M Mini pins

    The i.MX 8M Mini pins got up to 10 different functions. Only the more common used are listed.

    PIN

    Name

    Alt0

    Alt1

    Alt2 / Alt3

    Alt5

    19

    UART3_RXD

    ecspi1.SCLK

    uart3.RX

     

    gpio5.IO[6]

    21

    UART3_TXD

    ecspi1_MOSI

    uart3.TX

     

    gpio5.IO[7]

    22

    SPIN22_RTS3

    ecspi1.MISO

    uart3.CTS_B

     

    gpio5.IO[8]

    23

    UART1_DTR

    sai5.RX_SYNC

    sai1.TX_DATA[0]

     

    gpio3.IO[19]

    24

    SPIN24_CTS3

    ecspi1.SS0

    uart3.RTS_B

     

    gpio5.IO[9]

    25

    UART1_CTS

    uart3.TX

    uart1.RTS_B

     

    gpio5.IO[27]

    27

    UART1_RTS

    uart3.RX

    uart1.CTS_B

     

    gpio5.IO[26]

    29

    UART1_DSR

    sai5.RX_BCLK

    sai1.TX_DATA[1]

     

    gpio3.IO[20]

    31

    UART1_DCD

    sai2.RX_SYNC

    sai5.TX_SYNC

    sai5.TX_DATA[1]

    gpio4.IO[21]

    32

    UART2_CTS

    uart4.TX

    uart2.RTS_B

     

    gpio5.IO[29]

    33

    UART1_RXD

    uart1.RX

    ecspi3.SCLK

     

    gpio5.IO[22]

    34

    UART2_RTS

    uart4.RX

    uart2.CTS_B

    pcie1.CLKREQ_B

    gpio5.IO[28]

    35

    UART1_TXD

    uart1.TX

    ecspi3.MOSI

     

    gpio5.IO[23]

    36

    UART2_RXD

    uart2.RX

    ecspi3.MISO

     

    gpio5.IO[24]

    37

    UART1_RI

    sai2.RX_BCLK

    sai5.TX_BCLK

     

    gpio4.IO[22]

    38

    UART2_TXD

    uart2.TX

    ecspi3.SS0

     

    gpio5.IO[25]

    43

    SPIN43

    gpio1.IO[7]

    enet1.MDIO

     

    usdhc1.WP

    45

    SPIN45

    rawnand.CE3_B

    qspi.B_SS1_B

     

    gpio3.IO[4]

    47

    SD2_CLK

    usdhc2.CLK

     

     

    gpio2.IO[13]

    49

    SAI1_RXD0

    sai1.RX_DATA[0]

    sai5.RX_DATA[0]

    sai1.TX_DATA[1]

    gpio4.IO[2]

    51

    SD2_DATA3

    usdhc2.DATA3

     

     

    gpio2.IO[18]

    53

    SAI1_RXD1

    sai1.RX_DATA[1]

    sai5.RX_DATA[1]

     

    gpio4.IO[3]

    55

    SPIN55

    sai5.RX_DATA[0]

    sai1.TX_DATA[2]

     

    gpio3.IO[21]

    57

    SAI1_RXD2

    sai1.RX_DATA[2]

    sai5.RX_DATA[2]

     

    gpio4.IO[4]

    59

    SD2_DET

    usdhc2.CD_B

     

     

    gpio2.IO[12]

    61

    SAI1_RXD3

    sai1.RX_DATA[3]

    sai5.RX_DATA[3]

     

    gpio4.IO[5]

    63

    SAI1_RXD4

    sai1.RX_DATA[4]

    sai6.TX_BCLK

    sai6.RX_BCLK

    gpio4.IO[6]

    65

    SAI1_RXD5

    sai1.RX_DATA[5]

    sai6.TX_DATA[0]

    sai6.RX_DATA[0]

    sai1.RX_SYNC

    gpio4.IO[7]

    67

    SAI1_RXD6

    sai1.RX_DATA[6]

    sai6.TX_SYNC

    sai6.RX_SYNC

    gpio4.IO[8]

    69

    LED_GPIO

    sai3.MCLK

    pwm4.OUT

    sai5.MCLK

    gpio5.IO[2]

    71

    SAI1_RXD7

    sai1.RX_DATA[7]

    sai6.MCLK

    sai1.TX_SYNC

    sai1.TX_DATA[4]

    gpio4.IO[9]

    73

    SAI5_RXD1

    sai5.RX_DATA[1]

    sai1.TX_DATA[3]

    sai1.TX_SYNC

    sai5.TX_SYNC

    gpio3.IO[22]

    75

    SAI5_RXD2

    sai5.RX_DATA[2]

    sai1.TX_DATA[4]

    sai1.TX_SYNC

    sai5.TX_BCLK

    gpio3.IO[23]

    77

    BACKLIGHT_PWM

    gpio1.IO[1]

    pwm1.OUT

     

    anamix.REF_CLK_24M

    79

    POWERFAIL

    sai5.RX_DATA[3]

    sai1.TX_DATA[5]

    sai1.TX_SYNC

    sai5.TX_DATA[0]

    gpio3.IO[24]

    81

    SD2_DATA1

    usdhc2.DATA1

     

     

    gpio2.IO[16]

    85

    SD2_DATA2

    usdhc2.DATA2

     

     

    gpio2.IO[17]

    86

    FPGA_CIF_VSYNC *3)

    ecspi2.SS0

    uart4.RTS_B

     

    gpio5.IO[13]

    87

    RESET_OUT

    gpio3.IO[14]

     

     

     

    88

    SAI1_MCLK

    sai1.MCLK

    sai5.MCLK

    sai1.TX_BCLK

    gpio4.IO[20]

    90

    SAI1_RXC

    sai1.RX_BCLK

    sai5.RX_BCLK

     

    gpio4.IO[1]

    92

    SAI1_RXFS

    sai1.RX_SYNC

    sai5.RX_SYNC

     

    gpio4.IO[0]

    93

    SPIN93

    rawnand.WP_B

     

     

    gpio3.IO[18]

    94

    I2C1_SCL

    i2c1.SCL

    enet1.MDC

     

    gpio5.IO[14]

    95

    SPIN95

    rawnand.READY_B

     

     

    gpio3.IO[16]

    96

    I2C1_SDA

    i2c1.SDA

    enet1.MDIO

     

    gpio5.IO[15]

    98

    SPIN98

    gpio1.IO[0]

    ccmsrcgpcmix.ENET_PHY_REF_CLK_ROOT

     

    anamix.REF_CLK_32K

    100

    DISPLAY_ENABLE

    gpio1.IO[5]

    m4.NMI

     

    ccmsrcgpcmix.PMIC_READY

    101

    SPIN101

    sai3.TX_SYNC

    gpt1.CAPTURE2

    sai5.RX_DATA[1]

    gpio4.IO[31]

    102

    AUDIO_ENABLE

    gpio1.IO[8]

    enet1.1588_EVENT0_IN

     

    usdhc2.RESET_B

    103

    SPIN103

    sai3.TX_BCLK

    gpt1.COMPARE2

    sai5.RX_DATA[2]

    gpio5.IO[0]

    104

    SPIN104

    rawnand.DATA05

    qspi.B_DATA[1]

     

    gpio3.IO[11]

    105

    QSPI_SCLK

    rawnand.ALE

    qspi.A_SCLK

     

    gpio3.IO[0]

    106

    SAI5_MCLK

    sai5.MCLK

    sai1.TX_BCLK

     

    gpio3.IO[25]

    107

    QSPI_SS0

    rawnand.CE0_B

    qspi.A_SS0_B

     

    gpio3.IO[1]

    110

    SAI1_TXD0

    sai1.TX_DATA[0]

    sai5.TX_DATA[0]

     

    gpio4.IO[12]

    111

    QSPI_DATA0

    rawnand.DATA00

    qspi.A_DATA[0]

     

    gpio3.IO[6]

    112

    SAI1_TXD1

    sai1.TX_DATA[1]

    sai5.TX_DATA[1]

     

    gpio4.IO[13]

    113

    QSPI_DATA1

    rawnand.DATA01

    qspi.A_DATA[1]

     

    gpio3.IO[7]

    114

    SAI1_TXD2

    sai1.TX_DATA[2]

    sai5.TX_DATA[2]

     

    gpio4.IO[14]

    115

    PCIE_CLKREQ (*5)

    i2c4.SCL

    pwm2.OUT

    pcie1.CLKREQ_B

    gpio5.IO[20]

    116

    SAI1_TXD3

    sai1.TX_DATA[3]

    sai5.TX_DATA[3]

     

    gpio4.IO[15]

    117

    QPSPI_DATA2

    rawnand.DATA02

    qspi.A_DATA[2]

     

    gpio3.IO[8]

    118

    SAI1_TXD4

    sai1.TX_DATA[4]

    sai6.RX_BCLK

    sai6.TX_BCLK

    gpio4.IO[16]

    119

    QSPI_DATA3

    rawnand.DATA03

    qspi.A_DATA[3]

     

    gpio3.IO[9]

    120

    SAI1_TXD5

    sai1.TX_DATA[5]

    sai6.RX_DATA[0]

    sai6.TX_DATA[0]

    gpio4.IO[17]

    121

    SPIN121

    rawnand.DATA04

    qspi.B_DATA[0]

     

    gpio3.IO[10]

    122

    SAI1_TXD6

    sai1.TX_DATA[6]

    sai6.RX_SYNC

    sai6.TX_SYNC

    gpio4.IO[18]

    123

    CSI1_PWDN

    gpio1.IO[3]

    usdhc1.VSELECT

     

    sdma1.EXT_EVENT[0]

    124

    SAI1_TXD7

    sai1.TX_DATA[7]

    sai6.MCLK

     

    gpio4.IO[19]

    125

    CSI_RESET

    gpio1.IO[6]

    enet1.MDC

     

    usdhc1.CD_B

    126

    SAI1_TXFS

    sai1.TX_SYNC

    sai5.TX_SYNC

     

    gpio4.IO[10]

    127

    USB1_PEN

    gpio1.IO[12]

    usb1.OTG_PWR

     

    sdma2.EXT_EVENT[1]

    128

    SAI1_TXC

    sai1.TX_BCLK

    sai5.TX_BCLK

     

    gpio4.IO[11]

    129

    USB2_PEN

    gpio1.IO[14]

    usb2.OTG_PWR

     

    pwm3.OUT

    131

    USB2_OC

    gpio1.IO[15]

    usb2.OTG_OC

     

    pwm4.OUT

    132

    SPIN32

    rawnand.DATA06

    qspi.B_DATA[2]

     

    gpio3.IO[12]

    133

    USB1_OC

    gpio1.IO[13]

    usb1.OTG_OC

     

    pwm2.OUT

    134

    USB1_PD_INT

    rawnand.CE2_B

    qspi.B_SS0_B

     

    gpio3.IO[3]

    136

    USB1_SS_SEL

    rawnand.RE_B

    qspi.B_DQS

     

    gpio3.IO[15]

    146

    BT_PCM_IN *4)

    sai3.TX_DATA[0]

    gpt1.COMPARE3

    sai5.RX_DATA[3]

    gpio5.IO[1]

    154

    PCIE_WAKE

    rawnand.DATA07

    qspi.B_DATA[3]

     

    gpio3.IO[13]

    159

    SPDIF_IN

    spdif1.IN

    pwm2.OUT

     

    gpio5.IO[4]

    161

    SPDIF_OUT

    spdif1.OUT

    pwm3.OUT

     

    gpio5.IO[3]

    163

    SPDIF_EXT_CLK

    spdif1.EXT_CLK

    pwm1.OUT

     

    gpio5.IO[5]

    184

    BT_PCM_OUT *4)

    sai3.RX_DATA[0]

    gpt1.COMPARE1

    sai5.RX_DATA[0]

    gpio4.IO[30]

    186

    BT_PCM_CLK *4)

    sai3.RX_BCLK

    gpt1.CLK

    sai5.RX_BCLK

    gpio4.IO[29]

    188

    BT_PCM_SYNC *4)

    sai3.RX_SYNC

    gpt1.CAPTURE1

    sai5.RX_SYNC

    gpio4.IO[28]

    190

    SD2_CMD

    usdhc2.CMD

     

     

    gpio2.IO[14]

    192

    SD2_DATA0

    usdhc2.DATA0

     

     

    gpio2.IO[15]

    194

    I2C2_SDA

    i2c2.SDA

    enet1.1588_EVENT1_OUT

     

    gpio5.IO[17]

    196

    I2C2_SCL

    i2c2.SCL

    enet1.1588_EVENT1_IN

     

    gpio5.IO[16]

    1.2.2 Kinetis MCU pins

    Several pins are GPIOs which may be configured for different functions by software.

    Please check with the microcontroller datasheet for additional pin-mux information.

    PIN

    Name

    Alt0

    Alt1

    Alt2

    Alt3

    Alt4

    Alt5

    Alt6

    Alt7

    2

    VIN_AD3

    ADC0_SE7
    ADC1_SE7
    ADC1_DM1

    PTE19

    SPI0_SIN

    UART1_
    RTS

    I2C0_
    SCL

     

    SPI0_
    SOUT

     

    4

    VIN_AD2

    ADC0_SE6
    ADC1_SE1
    ADC1_DP1

    PTE18
    LLWI_P20

    SPI0_SOUT

    UART1_
    CTS

    I2C0_
    SDA

     

    SPI0_
    SIN

     

     

    6

    VIN_AD1

    ADC0_DM1
    ADC0_SE5
    ADC1_SE5

    PTE17
    LLWI_P19

    SPI0_SCK

    UART1_
    RX

    FTM_
    CLKIN1

     

    LPTMR0
    _ALT3

     

    8

    VIN_AD0

    ADC0_SE1
    ADC0_DP1
    ADC1_SE0

    PTE16

    SPI0_PCS0

    UART1_
    TX

    FTM_
    CLKIN0

     

    FTM_
    FLT3

     

    14

    TSPX

    ADC0_SE8
    ADC1_SE8

    PTB0
    LLWU_P5

    I2C0_SCL

    FTM1_
    CH0

     

     

    FTM1_
    QD_PHA

    UART0_
    RX

    16

    TSMX

    ADC0_SE9
    ADC1_SE9

    PTB1

    I2C0_SDA

    FTM1_
    CH1

    FTM0_
    FLT2

    EWM_IN

    FTM1_
    QD_PHB

    UART0_
    TX

    18

    TSPY

    ADC0_SE11
    CMP1_IN0

    PTC2

    SPI0_PCS2

    UART1_
    CTS

    FTM0_
    CH1

    FTM2_
    CH1

     

     

    20

    TSMY

    ADC1_SE4
    CMP1_IN4
    DAC0_OUT

    PTE30

     

    FTM0_
    CH3

     

    FTM_
    CLKIN1

     

     

    24

    SPIN24_
    CTS3

     

    PTA4
    LLWU_P3

     

    FTM0_
    CH1

    FTM4_
    FLT0

    FTM0_
    FLT3

     

    NMI_b

    26

    RESET_IN

     

    PTA20

     

     

     

     

     

    RESET

    97

    CAN1_RX

     

    PTE25
    LLWU_P21

    CAN
    _RX

    FTM0_
    CH1

     

    I2C0_
    SDA

    EWM_
    IN

     

    99

    CAN1_TX

     

    PTE24

    CAN0_TX

    FTM0_
    CH0

     

    I2C0_
    SCL

    EWM_
    OUT

     

    *) Only MKV11 MCU, not usable with MKV10 MCU.

    ADC_SE          Single-Ended ADC
    ADC_DM/P      Differential ADC
    LLWU              Wakeup-Sources
    EWM               External Watchdog Monitor
    FTM                 Flexible Timer Module
    FTM_CH          Output Channel
    FTM_FLT         Fault
    FTM_QD_PH   Quadrature Decoder

    1.3      Electrical Pin-Information

    PI:

    Power Input

     

    DO:

    Digital Output

    PO:

    Power Output

     

    DIO:

    Digital Input/Output

     

     

     

    DDI:

    Differential Input

    AI:

    Analog Input

     

    DDO:

    Differential Output

    AO:

    Analog Output

     

    DDIO:

    Differential Input/Output

     

     

     

     

     

    DI:

    Digital Input

     

    OD

    Open-Drain Output

     

     

     

     

     

    PD:

    Pull-Down

    (PDp: Pull-Down, Pull-behavior can be changed by software)

    PU:

    Pull-Up

    PUp: Pull-Up, Pull-behavior can be changed by software

    If two “types” are specified, the first value determines the type of primary function.

     

    SODIMM

    PIN

    Name

    Type

    Voltage

    Connected to

    1

    AUDIO_MIC_OUT

    AI

     

    Audio-Codec

    3

    AUDIO_MIC_GND

    AI

     

    Audio-Codec

    5

    AUDIO_LINEIN_L

    AI

     

    Audio-Codec

    7

    AUDIO_LINEIN_R

    AI

     

    Audio-Codec

    9

    AUDIO_AGND

    Analog Audio
    Ground

    Audio-Codec and VREF- of Kinetis MCU

    11

    AUDIO_AGND

    13

    AUDIO_HEADPHONE_GND

    AI

     

    Audio-Codec

    15

    AUDIO_HEADPHONE_L

    AO

     

    Audio-Codec

    17

    AUDIO_HEADPHONE_R

    AO

     

    Audio-Codec

    19

    UART3_RXD

    DI, DIO

    NVCC_3V3

    i.MX8M and BT module, if no FPGA (RA600)

    21

    UART3_TXD

    DO, DIO

    NVCC_3V3

    23

    UART1_DTR

    DO, DIO

    NVCC_3V3

    i.MX8M

    25

    UART1_CTS

    DI, DIO

    NVCC_3V3

    i.MX8M

    27

    UART1_RTS

    DO, DIO

    NVCC_3V3

    i.MX8M

    29

    UART1_DSR

    DI, DIO

    NVCC_3V3

    i.MX8M

    31

    UART1_DCD

    DI, DIO

    NVCC_3V3

    i.MX8M

    33

    UART1_RXD

    DI, DIO

    NVCC_3V3

    i.MX8M

    35

    UART1_TXD

    DO, DIO

    NVCC_3V3

    i.MX8M

    37

    UART1_RI

    DI, DIO

    NVCC_3V3

    i.MX8M

    39

    GND

    Ground

    41

    GND

    43

    SPIN43

    DIO

    NVCC_3V3

    i.MX8M

    45

    SPIN45

    DIO

    NVCC_3V3

    i.MX8M

    47

    SD2_CLK

    DO, DIO

    NVCC_3V3

    i.MX8M

    49

    SAI1_RXD0

    DI, DIO

    NVCC_3V3

    i.MX8M

    51

    SD2_DATA3

    DIO

    NVCC_3V3

    i.MX8M

    53

    i.MX8M

    DI, DIO

    NVCC_3V3

    i.MX8M

    55

    SPIN55

    DIO

    NVCC_3V3

    i.MX8M

    57

    FPGA_CIF_D2

    DI, DIO

    NVCC_3V3

    Fi.MX8M

    59

    SD2_DET

    DI, DIO

    NVCC_3V3

    i.MX8M

    61

    FPGA_CIF_D3

    DI, DIO

    NVCC_3V3

    i.MX8M

    63

    FPGA_CIF_D4

    DI, DIO

    NVCC_3V3

    i.MX8M

    65

    FPGA_CIF_D5

    DI, DIO

    NVCC_3V3

    i.MX8M

    67

    FPGA_CIF_D6

    DI, DIO

    NVCC_3V3

    i.MX8M

    69

    LED_GPIO, PWM4

    DO, DIO

    NVCC_3V3

    i.MX8M

    71

    FPGA_CIF_D7

    DI, DIO

    NVCC_3V3

    i.MX8M

    73

    FPGA_CIF_D8

    DI, DIO

    NVCC_3V3

    i.MX8M

    75

    FPGA_CIF_D9

    DI, DIO

    NVCC_3V3

    i.MX8M

    77

    BACKLIGHT_PWM

    DO, DIO

    NVCC_3V3

    i.MX8M

    79

    POWERFAIL

    DI, DIO

    NVCC_3V3

    i.MX8M

    81

    SD2_DATA1

    DIO

    NVCC_3V3