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    • JTAG CPLD programming

    Owned by Anu Selvaraj (Deactivated)
    Last updated: 13. Nov 2023 by Michael Schieren
    1 min read

    The following pictures show the pin assignment for programming Xilinx respectively Lattice CPLD's using Seco's JTAG debug PCB by Keith & Koep.

    Xilinx CPLD

    Lattice CPLD

    ( We use the „Diamond Programmer Version 3.12.0.240.2 and the HW-USBN-2A , both  provided by  Lattice)